Design Of 9-17GHz Fractional PLL For Multi-protocol SerDes

SerDes for high speed wireline communication has become a hot research topic.SerDes is the abbreviation of serializer and deserializer.On the transmitter or serializer side,it combines multiple parallel low speed data into one channel of serial high speed data stream,On the receiver or deserializer side it recovers the high speed data and seperates it into multiple parallel low speed data.In the SerDes system,a local oscillator or an on chip clock is needed on both the transmitter and receiver side.The important function of PLL is to use its feedback adjustment ability to generate a clock with stable frequency in response to various process deviations and temperature changes.The goal of this thesis is to design a PLL based clocking system which can support multiple protocols like PCIE4.0,Rapid IO,Fibre Channel and Ethernet based on umc28 nm CMOS technology.The contents of the thesis are as follows: the PLL loop theory and system noise are analyzed in detail,the PLL loop bandwidth is programmable to support a variety of crystal oscillator reference frequency at the PLL input.The advantages and disadvantages of various structures of the VCO are compared.On this basis,the optimal structure is selected,and a single VCO is designed,which can cover an ultra wide frequency tuning range of 9-17 GHz.The VCO gain variation caused by the wide frequency range is compensated by using the VCO varactor array.The test results show that it can achieve-96.5d Bc/Hz@1M at 12.5GHz output frequency.In order to maximize the input reference range the PLL can support,a multi-modulus divider with 9-bit digital control is designed to achieve an integer division ratio of 8-511.The fractional frequency division function is realized with the third-order DSM modulator.Finally,in order to achieve low output jitter,high-quality on-chip power management module is essential,this paper designed a high-performance voltage reference.The worst PSRR of the high performance voltage reference is-45 d B @10MHz.The average temperature coefficientis C)125-C40C@(-21.6ppm/???.In addition,low dropout linear regulator uses dual loop cascaded flipped voltage follower structure to realize fully on-chip integration.The LDO maximum output current can be configured according to different loading.The average bandwidth of fast response loop is 10 MHz,and the worst case PSRR under full load is-17.8d B@1.1GHz.