Design Of A Large Tuning Range And Fully Differential Phase-locked Loop For Application Of ADC Measurement

PLL is a kind of circuit which is widely used in modern communication systems and a variety of digital chips. Because of its versatility, PLL appears everywhere. Based on the principle of phase locking, phase-locked frequency synthesizer can be used as the application of clock generator in digital circuits. In the communication system, modulation and demodulation modules also need phase-locked loop to provide signals with same frequency and constant phase difference. In addition, as a phase-locked loop, clock recovery circuit is also an important application, among all others.The contents of this thesis mainly based on phase locking principle,to design a frequency synthesizer for the successive approximation type ADC as a clock signal used for measurement. Since in the measurement process the clock frequency varies in a large range, the focus of this thesis is how to design a phase-locked loop with wide tuning range.The main work of this thesis includes the adoption of system-level analysis and modeling, through which the technical parameters of each module in phase-locked loop are established; verification of its functionality with behavioral simulation; implementation of the main module in PLL, including the voltage-controlled oscillator, self-bias circuit, full-custom digital divider, PLL start-up circuitry and measurement circuitry, with transistor level circuit design.In the specific design, through the use of self-biasing technique, a wide tuning range and low power consumption voltage-controlled oscillator is designed. And through fair modeling, a loop filter that meets the stability and dynamic response of PLL is chosen. On this basis, a phase-locked loop with wide-tuning range which meets the specification is designed.