Design And Implementation Of High Performance Phase Locked Loop For High Speed Serial Interface

As important building block in wireless communication and high speed serial interface electronics systems, the phase-locked loop (PLL) has to meet critical requirements with low phase noise, agile response and low electromagnetic interference as the system is getting complex. Focused on the applications such as frequency synthesis and clock generation in high speed serial interface, the constant voltage-controlled oscillator gain, fast settling, noise optimization and duty cycle optimization are researched in this dissertation.Proceeding from the stability and phase noise of PLL, the operational principle of PLL is presented, and then loop parameters design procedure is described. The phase noise model of integer-N and△Σfractional-N PLL are proposed to provide theoretic supports for the noise optimization and circuits’design of PLL. The constant VCO gain method is proposed to mitigate the problem of large variation of VCO gain in PLL. And a wideband VCO frequency range of9.5-10.6GHz is implemented. A novel automatically frequency calibration technique is proposed, which can greatly decrease the calibration time and improve the calibration efficiency, thus meeting the goal of fast settling. The new duty cycle corrector circuit is employed to improve the signal quality and reduce the system jitter for PLL’s duty cycle optimization. In order to reduce the charge pump current mismatch and spurs, two charge pumps are designed in programmable structure to compensate the PLL bandwidth variation.An integer-N frequency synthesizer aiming at high speed serial interface is implemented in a SMIC55nm CMOS process. The chip area is0.33mm2. The measurement results show that the PLL operating frequency is5GHz, the AFC search time is about4.2μs and the overall locking time is less than15μs. The phase noise is-110.04dBc/Hz at1MHz and the power consumption is20mW. It obtains an ultra-low0.35ps random mean square jitter and achieves excellent performance.In terms of the issue of electromagnetic interference for high frequency clock, a spread spectrum clock generator is implemented in a Huali55nm CMOS process, which is based on the frequency synthesizer chip. The chip area is0.28mm2. The measurement results show that the SSCG operates at10GHz, the modulation frequency and frequency deviation of spread spectrum clock are30.525kHz and5000ppm, respectively. Phase noise is-106.17dBc/Hz at1MHz, and the peak reduction of electromagnetic interference is16.46dB while the power consumption is17.4mW. A high performance chip is implemented and the validity of the design is verified.