Research And Design Of High-speed,Low-power Divider For RF Ultra Wideband PLL

The wireless communications market has been thriving for the past two decades,and the development of communications technology has transformed our way of life.In recent years,the rapid increase of communication users and the rapid development of wireless communication technology have brought higher and higher requirements to modern wireless communication.Therefore,higher communication rates may be used to meet consumer,other industry and enterprise application requirements.Frequency synthesizer for generating various frequency band carriers in a transceiver system is still a big challenge to us.A frequency divider is a very important part in the high-frequency PLL frequency synthesizer.A divider module is the module that operates at the highest frequency and uses most of the power consumption of the PLL system.It also signficantly affects the phase noise performance of the entire PLL.The main content of this paper is the design of high-speed and low power consumption dividers including the design of multi-mode divider chain applied to 8-12 GHz multi-mode PLL frequency synthesizers and high-speed injection-locked frequency divider applied to 16-20 GHz PLL frequency synthesizers.In this paper,a SMIC 55 nm process was used to design a multi-mode divider chain for 8-12 GHz multi-mode PLL.The divider chain consists of a high-speed true sigle phase clock(TSPC)divided by 2 divider,four/five dual-modulus prescaler,divided by 8-15 multi-mode divider and low-speed divided by 2 divider.Since this paper used a more advanced process,a TSPC divider circuit could achieve a relatively high speed.Moreover,the low power consumption of the TSPC divider is particularly suitable for this design application.So this paper aims at the advantages and disadvantages of TSPC divider and designs a new type of high-speed TSPC divider.After analysis,this improved TSPC divider was the best compromise between speed and power consumption.The four/five dual-modulus prescaler was realized by this new type of TSPC divider and the low-frequency part which were multi-mode divider and low-speed divider was based on digital quasi-static D flip-flop.This paper can achieve 160,180,200,220,240 divider ratios with external control signals.The simulation results show ed that the circuit could realize the frequency division function at 8-12 GHz under the power supply voltage of 1.2V.Under normal conditions,the highest operating frequency the circuit could handle was 16.8 GHz.At the input frequency of 12 GHz,the frequency division ratio was 240,the output signal was 50 MHz,and the power consumption was 719.6?W,achieving high-speed and low-power technical indicators.Finally,this paper used SMIC 55 nm technology to design an injection-locked frequency divider for 16-20 GHz PLL.The injection-locked frequency divider is based on an RC loop oscillator.It uses a symmetrical injection circuit and a differential input to achieve multi-phase injection,thus achieving an ultra-wide lock range.The circuit has a quadrature output to meet the requirements of other circuits for four-phase clocks.Simulation results showed that when the input signal was 1V DC and the injected signal swing(Vpp)was 500 m V,the locking frequency of the injection-locked frequency divider was 12-24 GHz,the locking range was 13 GHz.When the input frequency was 18 GHz,the power consumption was 2.66 mW,which satisfied the design requirements for ultra-wideband low power consumption.