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Keyword [SerDes clock]
Result: 1 - 11 | Page: 1 of 1
1.
The Design And Verification Of The Clock Data Recovery Circuit In SerDes
2.
Design Of CDR And FFE In 20Gb/S High-Speed SerDes
3.
Design Of PLL Frequency Multiplier Applied In 3.125 Gb/s SerDes Transmitting System
4.
Key Technologies Research Of 12.5Gb/S SerDes Receiver And High-speed Low-power Demultiplexer
5.
Design Of Eight-phase VCO For High-Speed SerDes Application
6.
Research And Design Of Key Technologies Of SerDes Receiver
7.
Design And Implementation Of CPPLL Applied For 6.25Gbps SerDes
8.
Analysis And Design Of High-speed Clock And Data Recovery Circuit Base On 40nm CMOS Technology
9.
SerDes Interface Circuit Design Of Gigabit Ethernet
10.
Research On The Core Circuit Of CDR In High Speed SerDes
11.
Design Of 9-17GHz Fractional PLL For Multi-protocol SerDes
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