A Low-Voltage And Low-Power Fractional-N Phase-Locked Loop

With the continuous development of mobile medical technology,some wearable and implantable health monitoring devices have begun to spread.These devices rely on wireless communication systems for information transmission.However,it is difficult for these devices to obtain a continuously effective energy source,so a wireless communication system with low power consumption is required for normal use.As an important unit circuit in the wireless communication system,the phase-locked loop frequency synthesizer occupies a major part of the system power consumption.In addition,with the continuous development of the integrated circuit field,the feature size of the CMOS process is continuously reduced,and the supply voltage of the circuit design is continuously reduced.Therefore,a low-voltage and low-power phase-locked loop must be designed to meet the above development trends.This article expands on the low-voltage and low-power phase-locked loop,and completes the design of a low-voltage and low-power fractional phase-locked-loop chip.The key modules in this article are optimized for charge pump and VCO.The main work of this paper is including the following three aspects:First,the whole and the module of the phase-locked loop are studied in detail,and the S-domain linear time-invariant model of the phase-locked loop is established.The stability and dynamic characteristics of the loop are analyzed.In addition,by deriving the phase noise transfer function of the internal module of the phase locked loop,the phase noise transfer function of the phase-locked loop is obtained,which provides a theoretical basis for the phase noise optimization.Then this article proposes two main innovations.1.This paper presents a low-power and low-current-mismatch charge pump circuit based on dynamic current compensation.Through the accurate current replication structure based on resistance,the current mismatch of the charge pump circuit is reduced to less than 1%.At the same time,the proposed structure introduces an additional compensation current,which reduces the power consumption of the charge pump,and its power consumption is only 0.64m W.2.With low supply voltages,the low phase noise design of traditional Class B VCOs becomes very difficult.The Class C VCO is suitable for design under low voltage application.However,in practical design,Class C VCOs have problems of difficulty in start-up and phase noise sensitive to PVT changes.To overcome these problems,this paper proposes a dual digital loop control class C VCO with low power consumption and low phase noise.The amplitude control loop stabilizes the amplitude and reduces the sensitivity of the VCO to PVT changes.The adaptive bias loop adjusts the gate voltage of the cross-coupled pair to optimize the phase noise performance of the VCO.At the same time,the VCO can reliably start up under different PVT conditions.Based on the SMIC 0.18?m RF CMOS process,the design of the prototype VCO chip is realized,and the chip area is 1.05×1.05mm~2.Test results show that the phase noise of the VCO is-121.3d Bc/Hz@1MHz,and the overall power consumption is less than 1.45m W.For other modules of the phase-locked loop,such as digital delta-sigma modulator and frequency divider,this paper also conducts detailed research.Finally,based on the SMIC0.18?m RF CMOS process,a low-voltage low-power fractional phase-locked loop prototype chip is designed.The total area of the chip is 1.5×1.5 mm~2,and the minimum power supply voltage is 0.8V.The simulation results show that the four sub-bands of the phase-locked loop cover the output frequency range of 2.24-2.85 GHz,and the lock time is not higher than 60?s.The overall power consumption of the phase-locked loop is less than 2.66m W at 0.8V power supply voltage.The phase noise of the phase-locked loop at the 1MHz frequency offset is less than-120.1d Bc/Hz,and the phase noise performance offset caused by temperature and process corner changes does not exceed 2.8d B.