Design Of Low-voltage Fractional Divider

Fractional phase-locked loop,which has the advantages of high frequency resolution,fast switching speed and low phase noise,is widely used in the RF chip.The low voltage fractional phase-locked loop can serve the very low-power wireless communication module.The operating frequency of the fractional divider is limited by the low supply voltage,so it is the bottleneck and key to achieving low voltage phase-locked loops.The main works of this thesis are to design a low-voltage fractional divider which can be used in the GPS receivers.In this thesis,the development of fractional divider technology is reviewed.The working principle and the common architecture of fractional divider and ?? modulator are expatiated.According to the system model of fractional phase locked loop,the transfer process of the phase noise is analyzed.The low voltage multi-mode programmable divider is designed based on the TSPC structure,while a novel 2/3 divider unit and 8/9 prescaler are proposed.The 2/3 divider unit uses E-TSPC structure,when under the mode of divide 2,the unworked part of the circuit is cut off only through one mode control switch,which reduces the power consumption while ensuring the working speed.The 8/9 prescaler circuit achieves the maximum operating frequency equivalent with the first level 2/3 divider unit by avoiding the feedback delay which limits the working speed.Based on the optimization technique of ?? modulator,a comprehensive improvement scheme is proposed.The 16-bit input is divided into high 10 bits and low 6 bits.The low 6 bits pass through the first order modulator,then the results with the high 10 bits summed are transferred to the input of the third order MASH modulator.The pre-level quantization noise and output signal of the third-order MASH modulator are passed to the post-level at the same time,ensuring the random sequence of output while reducing its hardware overhead.Based on the TSMC 0.13?m CMOS process,the schematic and layout of the fractional divider are completed,and the digital-analog mixed simulation is carried out.The post simulation results show that under the 0.7V supply voltage the phase noise of the divider is below-161dBc@1MHz at each process corner.The current consumption of the overall circuit is less than 0.269mA.The test results show that the working frequency range of the fractional divider covers 1.3GHz-1.6GHz,which meets the design requirements.