Research Of Key Techniques In CMOS Phase-Locked Loop

With the rapid development of integrated circuit and communication technology, phase-locked loops (PLL) based on low cost CMOS process are used more and more widely in many areas. PLLs are required to have specific performance in different applications. It is difficult to design and optimize the key modules in PLL for specific application. In a mixed-signal system, the power-ground noise from digital modules is very serious. The frequency of the voltage controlled oscillator (VCO) will be modulated by this kind of noise, which means the performance of PLL is degraded. In high frequency PLLs, usually higher than 10 GHz, the design of high frequency divider is very important. It is difficult to achieve a divider circuit with low power, high frequency, wide locking range and high stability at the same time. In this thesis, detailed researches have been done for these two issues.In the research of power-ground noise issue in PLL, high supply sensitivity of VCO is the major reason of performance degradation. Compensation technique is a good option to reduce the supply sensitivity of VCO. In this thesis, the causes of high supply sensitivity in CML ring VCO are analysed. Detailed analysis and simulation are given for cross-coupled capacitance compensation and MOS varactor compensation techniques. A compensation strength self-calibration system is designed for better performance. And the calibration precision is accurately determined by the analysis of large-signal supply sensitivity.In the research of high frequency divider, CML-DFF divider is more attractive, due to its high stability and optimization potential. For this kind of divider, traditional analysis methods face many difficulties. In this thesis, a graphical analytical model for CML-DFF divider is established based on oscillation criterion and current vector analysis. The introduction of peaking inductor in CML-DFF divider is also considered in this model. Based on this accurate model, a frequency tunable CML-DFF divider with novel tuning technique is designed. Automatic frequency calibration technique is also studied for practicability.The major innovations of this thesis include:1) Novel VCO supply sensitivity compensation technique. Traditional compensation circuit is limited by complexity and bad versatility. The gate capacitor of MOS transistor has low capacitance and high changing rate. In the novel compensation circuit, this capacitor is applied as a varactor. This method has higher compensation efficiency and better versatility.2) Novel analytical model for CML-DFF divider. The optimization of CML-DFF divider is very difficult in traditional analysis methods. In this thesis, a graphical analytical model is established based on the combination of oscillation criterion and current vector analysis. This model is accurate and more intuitive. The model of CML-DFF divider with peaking inductor is also established.3) Novel frequency tuning technique for CML-DFF divider. Frequency tuning technique is widely used in oscillator-liked circuits. Traditional method is to change the load impedance of the circuit, which will introduce additional parasitic devices. In this thesis, transconduction ratio tuning method is applied due to the special working principle of CML-DFF divider. This method has advantages of less parasites and wider tuning range.Finally, a supply-insensitive PLL is designed in SMIC 180 nm CMOS process. Measurement result shows the large-signal supply sensitivity of CML VCO is reduced by more than 97%, and the deterministic jitter of PLL is reduced by more than 74%. Two frequency tunable CML-DFF dividers are designed in TSMC 90 nm CMOS process. Simulation results show locking ranges of 0.8 to 30 GHz and 3 to 46.5 GHz, respectively. And the power consumption are only 3.53 mW and 9.3 mW, respectively. A divider chain with automatic frequency calibration is also designed and simulated based on these dividers.