Research On The Key Circuits Of Silicon-Based Wideband Fractional-N Phase-Locked Loop

The frequency synthesizer is a key component of the transceiver,and its performance is an important factor that affects the pros and cons of the entire system.The past decade have seen an increase progress in 5G technology.Low phase noise and fast locking are required for wideband frequency source.However,due to loop stability and other issues,there is a complex trade-off between the lock time of the frequency synthesizer and the frequency resolution and phase noise.Therefore,this thesis focuses on this difficulty,research and design a broadband fractional phaselocked loop frequency synthesizer.The research background and significance of fractional PLL are described,and the key modules of PLL are analyzed according to the linear time invariant model in S domain,and the frequency resolution of the integer-type phase-locked loop is determined by the loop.The limitation of bandwidth limitation and the analysis of the principle of fractional frequency provide a theoretical basis for the design of each module.This thesis designs a broadband fractional phase-locked loop frequency synthesizer based on 45 nm SOI technology.The main modules include voltage controlled oscillator,fractional frequency divider,frequency phase detector and output frequency division link.The voltage-controlled oscillator is the key module of the phase-locked loop.In this design,a switched capacitor array is used to expand the working frequency band.On the basis of the traditional cross-coupling structure,a separate bias method is used to optimize the phase noise,and it is proposed to add a source resistance to improve the transconductance of the transistor linearity,increase the symmetry of the output waveform,and thereby reduce the phase noise.The simulation results show that the VCO frequency range is 5.0GHz-5.8GHz,the tuning range is 14.8%,and the best phase noise is-124.3d Bc/Hz@1MHz.The fractional frequency divider is divided into two parts of the multi-mode frequency divider and the delta-sigma modulator.The multi-mode frequency divider is composed of a high-speed divide-by-2 unit and a divide-by-2/3 unit composed of SCL structure.The delta-sigma modulator adopts the MASH1-1-1 structure to modulate the quantization noise to high frequency,reducing in-band noise and spurious,and combining the SPI module and the delta-sigma modulator to reduce the number of PADs.The simulation results show that the coverage range of the multimode frequency divider is 650MHz-20GHz.When the input frequency is 20GHz,the minimum input swing is 96m V,which can achieve a frequency division ratio of 1024-2047,and the output swing reaches 0.55-1V,which has a good drive.ability.Testbench stimulus files are written to test the delta-sigma modulator,and the verified functions are in full compliance.The frequency discriminator adopts the classic edge-triggered structure,and the designed feedback delay loop eliminates the phase discrimination dead zone.The simulation results show that the detectable phase difference of the frequency phase detector is [-1.94?-1.94?],there is no phase detection dead zone,and the frequency division link working range is 4GHz-12 GHz.