Design Of PLL Frequency Multiplier Applied In 3.125 Gb/s SerDes Transmitting System

In order to satisfy people’s growing demand for the flow of information, serial communication technology SerDes with the advantages of low cost, large capacity, high speed, the strong anti-interference ability becomes the mainstream of high-speed interface technology and be used widely. This paper designs a clock generator which is an important module of the SerDes transmit system and implemented by TSMC 0.18 μm CMOS technology. Its main effect is providing clock signal for a 3.125 Gb/s SerDes transmit system.The clock generator designed in this paper is based on the structure of charge pump phase-locked loop, the frequency of the reference clock is 156.25MHz and the frequencies of the output are 312.5MHz and 1.5625 GHz. The digital circuits and the output buffer circuits implemented by the CMOS logic structure, by this way the power consumption of these circuits is reduced. On base of the phase dead area is eliminated, the frequency phase detector is realized by the D flip-flop and the NOR logic gate to reduce the feedback delay and the blind area scope. A gain promotion circuit is adopted in charge pump to increase the output resistance, decreasing the current mismatch. The voltage controlled oscillator is in a triple ring structure. The delay unit has differential inputs and outputs, what’s more, it applies positive feedback latch. By this way, the output wave converse more quickly and symmetry better, then the phase noise is suppressed more severely. The divider’s frequency dividing ratio is decided by the structure of serializer. The divider proposed in this paper should be divided by 5at first, outputting a clock whose frequency is 312.5MHz and the duty cycle is 20%, then, it is divided by 2, outputting a clock whose frequency is equal to the reference clock.The area of the chip is 0.395mm× 0.495mm. The power supply is 1.8V and the load is 50Ω The post-simulation results show that the core power consumption of the charge pump phase locked loop is 5.4mW when it operates at 1.5625GHz in TT process corner. The locking time is less than 400ns, the peak of output is 331mV. The test results shows that the lock range of the phase-locked loop is 1.499GHZ-1.974GHz, the RMS jitter is 1.997ps and the power consumption is 25mW.