RF Phase - Locked Loop Based On Time Window Phase And Phase / Voltage Conversion And Millimeter - Wave Oscillator Based On Metamaterials

The growing demands for PLL designs with low power, low reference spur and low phase noise have been explored recently for varieties of applications such as frequency synthesizers, communication systems and RF transceivers. A2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this thesis. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal amplitude close to zero in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. Due to the APD, the dividers in the proposed PLL can be turned off in locked state, eliminating the power and noise contributions from the dividers. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard TSMC0.13μμm CMOS process. It consumes2.5mA from a1.2-V supply voltage and occupies a core area of0.48mm x0.86mm. The reference spur of the proposed PLL is measured to be-80dBc/-74dBc and an in-band phase noise of-103dBc/Hz at100kHz offset is achieved.In recent years, with the development of modern deep-submicron CMOS technology, it becomes feasible to realize mm-wave integrated circuits for high-data-rate wireless communication systems. As the critical building block in transceivers, oscillator is of the greatest importance for the whole system. The phase noise of oscillator depends on the quality factor (Q) of the resonator. In mm-wave operation regime, due to the passive device loss of substrate and metal interconnects, the Q value of the traditional LC-tank resonator suffers from a serious degradation, which leads to a high phase noise. In this thesis, a CMOS mm-wave oscillator using the differential metamaterial transmission line loaded with stacked split ring resonator (SRR) structure is presented for the improvement of the phase noise. Compared with the conventional CMOS LC based resonator, the proposed CMOS resonator using the SRR structure can enhance the EM energy coupling and further improve the quality factor, which improves the phase noise of the CMOS oscillator. The proposed CMOS oscillator is implemented in STM65nm RF-CMOS process, which consumes2.7mA from a1-V supply voltage and occupies a compact die area of0.38mm x0.32mm excluding PAD. For a76GHz resonant frequency, the measured phase noise of the proposed oscillator is-108.8dBc/Hz at10MHz offset and the figure-of-merit (FOM) is-182.1dBc/Hz.