Research On Charge Pump Phase Locked Loop Technology In High Speed SerDes Circuit

With the rapid development of integrated circuits and communication technologies,traditional parallel data transmission can not meet the current long-distance high-speed data transmission needs,and the serial interface Ser Des has gradually become the mainstream of high-speed interface technology.As the core part of Ser Des,serializer and clock recovery circuit need accurate clock generation circuit support,and the jitter size of the clock signal directly affects the performance of the serializer and clock recovery circuit.Charge pump phase-locked loop has the advantages of convenient integration,fast lock,low power consumption,low jitter,large frequency capture range and small static phase error,etc.The article introduces the development process and background of the phase-locked loop,and then analyzes the structure and basic working principle of the phase-locked loop.Secondly,it introduces the influencing effects and solutions that will be encountered in the design process on the circuit performance.Then the function of the noise source of each module of the phase-locked loop transmitted to the output is derived,and based on this,the noise is optimized from the perspective of design.After the systematic theoretical analysis,the five basic modules of the phase-locked loop are analyzed and studied in depth.The content of this subject design is:based on the SMIC 55nm process,the design of a low noise,fast locking of high-performance phase-locked loop PLL.It is mainly used as the clock source of the Ser Des transmitter chip with a data rate of5Gb/s to realize multi-frequency and multi-phase parallel output.The main innovations are as follows:(1)First,a delay circuit is added to the design of the frequency discriminator to solve the"dead zone"effect,so that when the input signal is in the same frequency and phase,the circuit will still output a narrow pulse to make the subsequent charge pump always open.(2)The non-ideal effect of charge pump charge sharing will cause the output voltage Vout to jitter.In response to this problem,this article uses a unity gain amplifier to reduce the charge sharing effect.(3)In the design of the voltage-controlled oscillator,in order to obtain a relatively large output frequency range without increasing the voltage-controlled oscillator gain _th,this paper uses a switched capacitor method to divide the output frequency band into several sub-bands,and select the sub-bands through algorithms.The smaller gain _thcan cover each sub-band.Then through the analysis of the loop transmission characteristics,more optimized index parameters are set,and the low jitter clock that meets the system requirements is output under this process.Then use Cadence Spectre software to complete circuit construction,simulation and layout design,and realize tape-out.Based on theoretical analysis and circuit design,a phase-locked loop with a core chip area of 0.54mm²and power consumption of 38m W was finally realized.The test results show that the output frequency covers 4.6?5.6GHz,the phase noise at 1MHz frequency deviation is around-110d Bc/Hz,and the RMS jitter and peak-to-peak jitter are 2.87ps and 13.4ps,respectively.