Novel systematic phase noise reduction techniques for phase interpolator clock and data recovery

This work focused on high-speed source-synchronous clock and multi-channel data receivers for inter-chip communications. Designs of inter-chip communication are becoming increasingly difficult with the rise in clock rates and the reduction in voltage supplies. Data transmissions at rates of gigabits per second require a fast and accurate clock and data recovery system on the front end of receivers.;Many designs allow for source-synchronous clocking architectures, but this work focused on a dual-loop with a phase-locked loop for frequency tracking and phase integrators for tracking each individual data lane. Limitations with the phase interpolator architecture cause systematic jitter, reducing the data eye.;Various techniques exist that aim to reduce or eliminate this systematic jitter from phase interpolator architectures. A technique based on digital lock detection was developed for this work that eliminates the phase interpolator systematic jitter.