Analysis And Design Of High-speed Clock And Data Recovery Circuit Base On 40nm CMOS Technology

With the rapid development of mobile Internet and Internet of Things,more and more information is transmitted over the internet,and improving the data transfer speed enable people to get information more quickly and improve work efficiency.Traditional parallel communication technology needs to tansmit data signals and clock signals synchronous,with the continuous increase of the data rate,it means require a large amount of transmission medium,it is difficult to minimize the skew between clock and data in the circuit design besides,SerDes as the mainstream technology in serial communication technology can achieve the data transmission with high date rate which replace the tranditional parallel communication technology.SerDes consist of a transmitter and a receiver and transmission medium,clock and data recovery(CDR)circuit is one of the crucial cuicuits of receiver,its main fuction is recover the synchronous clock to sampler the data received by receiver,and recover the correct data.Clock and data recovery circuit is a critical circuit in SerDes,its data rate determine the SerDes' s data rate.This paper presents the analysis and design of a high-speed clock and data recovery circuit base on 40 nm CMOS technology.First,based on overall analysis of the pros and cons of main stream CDR architectures.The CDR based on PS/PI circuit architecture can realized multi-channel share a common clock and locked in a short time,besides,the jitter is lower,so we choose the PS/PI CDR architecture to design a half-rate and high-speed CDR circuit.Next according to the theoretical derivation,the recovered clocks have a good linear relation when the PS/PI circuit use the linear coding and phase interpolation interval is 45°,so it is beneficial to design a 8 bit PS/PI circuit and its phase resolution is 1.4°.Finally,the design of CDR's phase detector is based on the Alexander bang-bang phase detector's phase discrimination principle,by improving the phase detection algorithm to adjust the high speed circuit;and the CML to CMOS circuit with a bandwith between 13 MHz and 103 MHz by using the AC-coupled inverter with a resistive feedback structure,it can detecting and amplifying the PS/PI circuit's small output differential clock signals to full swing clock signals;and we design a analog sampler circuit with sampling sensitivity of 60 mV,which can sample the data correctly at 7GHz clok signals.The CDR circuit's spectre simulation and analysis are completed by Cadence's Virtuoso,the post-simulation presents the recovered clock deterministic jitter is 3.73 ps and the eye diagrams of recovered data is 0.96 UI at TT corner.The CDR loop locked less than 1us,The CDR consumes 83.7mW at 14 Gbps.