Single Event Transient Effect And Its Mitigation In PI-based CDR

With the development of aerospace industry,the main frequency of radiation-hardened integrated circuits in equipments is increasing,and the demand of data bandwidth is increasing too.Some information processing platforms on satellites like navigation or optical image processing modules,are based on high-speed serial transmission architecture such as RapidIO and PCIE.SerDes which is the physical layer of these architectures trends towards more advanced technology and higher performance.The soft errors induced by single event transient(SET)are more and more serious as technology scales down.At the same time,the soft errors induced by SET are more and more evident as the frequency raises.So the studying of SET in SerDes is of great significance.The receiver with PI-based clock and data recovery(CDR)is an important part of SerDes,which is a typical analog-digital mixed circuit with high frequency.However,the SET characteristics of it are not widely studied.Using pulse laser and heavy ion experiments,we study the characteristics of the SET and its impact on the system level.Three hardening methods including“state rolling back logic”,“balance transmission gate”(BTG)and“off-state gate”are proposed.The hardened chip is implemented and verified successfully.The main works and contributions of this dissertation are as follows:(1)The pulse laser scanning experiments are carried out on a SoC chip with PI-based CDR.The methods of“active focusing based on adjustment of Z-axis”and“zero-coordinate setting on flip-chip SoC”are proposed to increase the accuracy of sensitive area.Through the experiments,it is discovered that the phase interpolator and the high-speed sampler are sensitive to pulse laser and CDR finite state machine(FSM)is more sensitive than the former.(2)The digital pulse injection is proposed to simulate SET in system level,and the state rolling back logic is put forward.Based On the 2nd order CDR,this dissertation implements the simulation of single event injection in CDR FSM and analyzes its effect on the closed loop feedback system.The results show that the accumulators in CDR FSM are the most sensitive module.The state rolling back logic can eliminate SET pulse which results that the eye diagrams of the recovery clock close partly and the menthod also can reduce the long recovery time under radiation.The method has no effect on the jitter of the recovery clock and can be applied to other orders CDR.(3)BTG hardening method is proposed to harden the high speed sampler.Three-dimensional mixed simulations are carried out on all transistors in the high speed sampler.The results show that the NMOS of two coupling inverters are the most sensitive MOSFET.The simulation results also show that the SET characteristics are related to the clock edge.“Edge sensitivity”is presented to characterize this issue.By using BTG,the LET threshold of the most sensitive node increases 10 MeV-cm~2/mg,while the edge sensitivity decreases 20%.(4)The off-state gate technique is proposed to mitigate the SET effect in the phase interpolator.The common mode rejection characteristics of the differential analog circuit are utilized.The mixed simulations show that the method decreases the number of the affected clock edge by 2/3 and the maximum phase offset is reduced by 58.3%.Charge sharing in the off-state gate structure is 64%higher than that in the traditional DCC structure,while the layout area is only 57.6%of the latter.(5)The SET hardened chip is implemented and verified successfully.Three hardening methods including“state rolling back logic”,“BTG”and“off-state gate”are used in the chip.The chip also includes controlling module which is applied for upper monitors to set parameters of running or read running informations.The dissertation also plans and discusses the unfinished work about the design of testing system and the pulse laser experiment on the harden chip.The dissertation studies the SET characteristics of PI-based CDR through single event experiments,system level simulation,circuit level simulation and device level simulation.The outcome of this study can give guidelines for the analysis and harden of other high-speed analog-digital mixed circuits.The digital pulse injection method has the advantage of convenient implementation and fast simulation speed.It can be extended to analyze the SET of other complicated mix-mode circuits.The state rolling back method has the advantage of fast recovery speed and has no influence on eye diagrams.It can be extended to other CDR with different orders.The off-state gate technique which exploits common mode rejection characteristics of analog circuits can provide harden guidance to other differential analog pairs.