Research And Design Of The Clock And Data Recovery Circuit In LVDS Receiver

Low-Voltage Differential Signaling (LVDS) transfers data using high speed differential signal with a low voltage swing, which can achieve a point-to-point or point-to-multipoint connections. Since it has many advantages such as low power, low BER, low crosstalk and low radiation, it can be helpful to solve the bottleneck problem of high speed data transferring in extensive application fields. LVDS receiver has become the star of the high speed I/O interface chip research.In this paper, the research and design of a LVDS receiver applied in Flat Panel Display is demonstrated. We design the chip by means of"top-down"and"bottom-up"mixed technique. Firstly, according to the functions the IC should have, the structure of the system is determined. The data eye's effective sampling margin is degraded by the effect of jitter and skew during the transmission, which may lead to sampling error. A receiver is designed to handle this jitter and skew and recover the correct sampled data.We divide our receiver into Deskew module, Clock and Data Recovery module and Sampling & Serial to parallel (S2P) module based on the analysis. Secondly, we work on the design of receiver's sub-blocks. Finally, the whole chip simulation and verification are conducted. This paper puts emphasis on the design of CDR circuit, so we present a detailed description on the design of Edge detector, Phase Interpolator (PI) and Sampling Clock Generator in our receiver; corresponding simulation result and analysis are also shown in the paper.On the basis of above research, the analog part is designed in TSMC 90 nm Mix-Signal Salicide(1.2V/3.3V) and digital part is designed in TSMC 90 nm tcbn90lphp process repectively, and simulation of whole chip's performance is done as well. Simulation result shows that the receiver can support a maximum data rate of 1.2 Gbps each channel, the toleration of skew and jitter can be up to±250 ps, meanwhile, the receiver can generate a disable signal to shutdown certain modules during lower frequency which lead lower power consumption. Simulation result shows that circuit works very well and meets the target specification which proves a successful design.