Design Of Multichannel And Hign-speed Clock And Data Recovery Circuit

With the rapid development of communication technology, the swift transmission of huge amounts of data like super computer, intelligent terminal, and multimedia network, users has put forward higher requirements for the data transmission. Because the serial communication has merits of high speed, it has gradually become the mainstream technology of the interface. IEEE 802.3 ae protocol has defined a high-speed and flexible signal transmission mode. With multi-channel XAUI(10 Ggigbit Attachment Unit Interface), 8/10 bit encoding is made for the signal, 10 Gbps data communication is completed. CDR(C lock and Data Recovery) is the most key circuit in the field of serial communication technology, also the bottleneck of ascension in the rate of high-speed interface. It works in the physical layer of the protocol, completing the generation of clock and retiming of data, which has played a decisive role in the performance of the whole communication system.This thesis based on standard SMIC 0.13 μm CMOS process, using the top-down design method, constantly optimizes the loop of CDR and unit circuit, and completes high-speed CDR circuit design with four channels and the total effective rate of 10 Gbps. The main content of this topic is:1) It has made a theoretical analysis of PI(Phase Interpolator) circuit in detail, discussing the weighting factors of PI respectively by dividing them into linear and nonlinear ones, so as to find a kind of nonlinear weighting factor which can make phase of output signal of PI have extraordinary linearity. At the same time, it has discussed interaction among the risetime of the input signal of PI, the phase difference of the input signal and time constant of output node, and their impact on the PI linearity.2) For the CDR circuit this time, four channels are chosen according to the interface standards of XAUI, each channel sharing reference clock provided by PLL circuit. With CDR circuit of analog quadrature-phase interpolation structure adopted, it has not merely improved the precision of minimum phase jump o f PI, also suitable for high speed circuit. In circuit design, the appropriate improvements have been made to the loop, with differential to single-ended circuit joined, and the jitter of peak-to-peak value of recovered clock has been reduced. Then, accord ing to the design requirements of circuit design in each unit, the halt-speed Alexande phase detector and the differential charge pump are selected in circuit design. The resistors of PI circuit are achieved with PMOS symmetrical load.Layout of CDR circuit covers an area is 532 μm * 426 μm. The length of the pseudo-random bit sequence(PRBS) is 223-1 from a single channel, and the baud rate of data is 3.125 Gbps. The simulation results show that locking time under slow-slow process corner is 6.2 μs; peak-to-peak jitter of restoring clock signal is 28.8 μs; maximum power consumption under the fast- fast process corner is 17.2 mW, this design meets the requirements.