Design Of Phase Interpolator In 3.125Gbps CDR Of High-Speed Serial RapidIO

In the widely used serial communication, the data will be transmitted from transmitter to the receiver without a synchronous clock. The received data suffer from asynchronous and noise effects . To recover the data, the system needs to extract a clock and use it to synchronize and"clear"the data. This system is called clock and data recovery (CDR). However, the received data accumulates jitter and noise during transmission. To recover the data correctly and decrease the bit error rate (BER), the extracted clock needs to track the phase of received data timely and accurately. Thus, adjusting the phase of the recovery clock based on the received data is a chief function in a CDR system.The phase interpolator is the most critical module in CDR. The nonlinearity of phase interpolator will directly affects the dynamic characteristic of CDR, even leads to error. While a frequency difference exists between the input data and the local clock, it also affects the jitter tolerance of CDR. Many of the timing problems related to high-speed signalling are mitigated through the use of phase-interpolating circuits to generate precise clock phases.The paper based on the interpretation of RapidIO interconnect architecture, with regard to the performance requirements of CDR, successfully explored a circuit of PI with the 0.13um CMOS technology, which is mainly applied to the 3.125Gbps CDR under high-speed serial RapidIO. The major contents and highlights of the research are as follows:(1) Through the study and comparison of several different kinds of CDR, and with consideration of the maximum design limits of speed, jitter and stability , the paper employ a CDR which based on PLL structure.(2) Explore a high precision phase interpolator. Testing results show that the phase interpolator has a monotone output phase and good linearity. The power dissipation of the phase interpolator is less than 9mW with a 3.125GHz/s work frequency.(3) The experimental result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases, which results in the nonlinearity of the phase interpolator. A new encoding pattern is given to solve this problem.(4) With the high-speed analog circuit layout guidelines, completed the layout design with the 0.13um CMOS technology. The Hspice simulation results show the phase interpolator we proposed well meets the project design requirement.