Research And Design Of Phase-Interpolator-Based Fractional-N Frequency Divider

In recent years,the rapid development of integrated circuits,the CMOS technology node has been shrinking,and the power consumption of the device has been reduced,which makes it possible to reduce the power supply voltage and power consumption of the circuit.In RF or microwave systems,the frequency synthesizer acts as a key module of the RF front-end chip,which can generate stable,programmable,low-noise local oscillator signals for use by different standard wireless transceivers.Its performance impact even determines the performance of entire wireless.transceiver system.In a phase-locked-loop(PLL)based frequency synthesizer,the frequency divider is one of the most important modules.In order to achieve smaller frequency steps and less system noise,a fractional-n frequency divider is introduced instead of an integer divider.Based on the research background and significance of the fractional divider,this thesis analyzes and introduces the design basis of the fractional divider,including the classification,structure,implementation principle and performance parameters of the PLL.The emphasis is on the fractional-n frequency divider in the PLL.Including the implementation principles,performance improvements,spurious generation and correction,and Sigma-Delta modulation techniques.Based on the CMOS SMIC 55 nm process,a fractional-n frequency divider based on phase interpolation was studied and designed.The main research contents and innovations of the thesis are as follows:Research and design of fractional-n frequency divider based on phase interpolation and CMOS SMIC 55 nm process.In the conventional fractional frequency divider,the average frequency division ratio is obtained by changing the instantaneous frequency division mode of the frequency divider to achieve fine frequency resolution.This method not only applies jitter when switching,but also has a large quantization noise,and an additional calibration circuit is required.Therefore,in order to achieve high frequency resolution,a high linearity,low power 8-bit phase interpolator circuit(PI)is first designed.By changing the phase of the input signal of the integer divider,the fractional division is directly realized.The application of integers between 1/28,compared to the traditional scheme,greatly reduces the power of quantization noise generated for jitter,does not require additional calibration circuits,achieves lower spurs,and higher phase shift accuracy.Then based on the phase interpolator,the overall architecture of the fractional divider is given to achieve true fractional division.The designed phase interpolator realizes the phase interpolation of the 2.4 GHz sinusoidal signal under the 1.2 V supply voltage.The interpolation precision is less than 2 ps.When the input signal amplitude is 20 m V,the output signal amplitude can reach 98 m V,which has a small Phase error with good gain and linearity.Together with the digital control module,the true fractional division can be realized.When the input signal frequency is 2.4 GHz,the integer division is 4,and the decimal place is 0.246,the input signal can be divided by 3.754.The average output frequency of the simulation output signal is 638.96 MHz with an error of 0.36 MHz.