Research On Circuit Technology Of High-Speed Serial Receiver

With semiconductor technology according to Moore’s law development,the scale of integrated circuit rapidly expanded,as well as the chip working frequency greatly improved,and promote the development of network technology day by day.At the same time,in today’s 5G communications,the amount of data transmitted between systems has increased dramatically,and the transmitting ability of data interfaces has become a major factor hindering system performance.The demand for the bandwidth of data communication between chips in the electronic device system is also increasing.The traditional parallel transmission technology is affected by the performance of I/O interface,and it is easy to produce crosstalk,clock skew and other phenomena in high-speed communication,which makes it difficult to further improve the data rate of parallel transmission technology.The high-speed serial communication interface has replaced the parallel interface as the main chip communication interface because it can greatly reduce the chip packaging pins and chip cost and board-level wiring.The main function of SerDes chip is to convert the parallel signal inside the sending chip into the high-speed serial signal by serial paralleling,and then the receiving end recovers the clock and data from the data stream containing noise and converts the data into the parallel signal after sampling the data at the appropriate phase.Firstly,the structure of SerDes system and the non-ideal characteristics in the channel are studied,and the channel modeling method under the application condition of SerDes is proposed.The common backplane communication channels are classified according to the components on the transmission path,and then the channels are modeled and simulated according to ESD model,package model,transmission line theory,parallel board theory and multi-port network.The continuous time equalizer(CTLE)and clock data recovery circuit(CDR)based on deep submicron process are researched and designed comprehensively.A 12.5Gbps high speed serial receiver based on TSMC 65 nm CMOS process is proposed.FR-4 material is usually used as a channel for high-speed serial interface in printed circuit boards.Due to the skin effect,dielectric loss and crosstalk coupling,the frequency-dependent insertion loss in the serial link channel has become the main limiting factor for the speed of high-speed serial interface and the further improvement of long-distance transmission.In order to maximize the bandwidth utilization of the channel and improve the performance of the transmission system,equalization techniques such as decision feedback equalizer(DFE)or continuous time equalizer are used to compensate for the non-ideal characteristics of the receiver.Aiming at the JESD204 B standard high-speed serial interface,the equalizer designed in this paper is a continuous time equalizer.A 12.5Gbps continuous time linear equalizer(CTLE)circuit composed of two-stage equalizer and three-stage limit amplifier is used to compensate the channel signal loss in the front end of CDR(clock and data recovery)circuit.The first level equalizer utilizes attenuation RC to compensate the low pass response and high frequency signal loss of the channel,and Inductive Shunt Peaking technology to further expand the bandwidth of the input signal.After the parasitic parameters were extracted and simulated,the peak-to-peak jitter of about 20 ps,voltage swing of 1.08 V and data rate of 12.5 Gbps were achieved through the wiring of a 10-inch FR4 PCB,and the equalization power consumption was low.Compared with DFE,CTLE is more suitable for serial communication systems with strict requirements on bit error rate and power consumption.The clock and data recovery circuit is the key part of high-speed serial interface.It can recover the clock and data information from the serial data stream in noisy channel at low bit error rate(BER),and resets the data signal to the best sampling position.The 12.5Gbps serial receiver proposed in this paper has two CDR loops sharing a PLL clock source.Each CDR circuit is composed of six parts,respectively is phase interpolation(PI),binary phase detector(BPD),random walk(RWF),adder,logic control logic to complete phase calibration between data reconciliation of serializer,with simple CML and CMOS logic,only make the design simple,more to the change of process,voltage and temperature fault tolerance.A phase-locked loop shared by two channel generates the orthogonal clock phase and assigns a high-frequency clock to each CDR for data recovery.Compared to the phase-locked loop based CDR(which requires charge pumps,analog filters,and VCO to calibrate the phase to optimize the sampling point),the two-loop phase interpolator(PI)-based CDR topology provides higher system stability,simple architecture,low power consumption,faster acquisition,and jitter peak locking.At the same time,in the source asynchronous scenario,the PI-based CDR can work over a wide range of data rates,with a certain allowable frequency offset between the sender and the receiver.After the circuit design of Serdes receiver is completed,the layout design of the circuit is also completed,and the chip layout is finished.The entire Serdes circuit is implemented using 65 nm CMOS process,and the chip area is 1.3mm~2.The post-simulation results show that the capture range of the CDR is from 3.125 Gbps to 12.5 Gbps at a power supply of 1.2V,and the power consumption is 300 mW.The proposed dual-channel receiver provides low voltage,low power consumption capability for backboard up to 12.5Gbps high-speed link communication.