Research On Pi-based Clock And Data Recovery Circuit For High-speed HDMI Interface

With the rapid development of the Internet of Things,the demand for high-speed communication in modern society is increasing.The high-speed serial communication technology,namely Serial-Deserializer(Ser Des)has been widely used due to its powerful data transmission capabilities and has become the current mainstream communication method.The clock data recovery circuit(CDR)is one of the most critical modules in the Ser Des system.Its function is to recover the clock signal from the high-speed input data at the receiving end and resample the input data.The performance of the CDR circuit directly determines the quality of the recovered clock and data,which in turn affects the performance of the entire Ser Des system.Based on the TSMC12nm process,this thesis uses a top-down design method to design a phase interpolation CDR circuit applied to high definition multimedia interface.First,the topology of the CDR needs to be determined on the basis of comparing the structure,performance,advantages and disadvantages of various types of CDR circuits.A CDR based phase interpolation with strong jitter suppression capability,large frequency difference tracking range,small impact by PVT changes,and multi-channel shared clock can be realized.Then Simulink is used model the CDR circuit to analyze the structure and working principle of the CDR circuit.And the key parameters of the CDR loop is simulated,such as the influence of the proportional path coefficient K_p and the integral path coefficient K_i on the circuit performance.By modeling the CDR circuit,the design time of the transistor-level circuit is greatly reduced.After the modeling is completed,the specific design and simulation verification of the CDR circuit based on phase interpolation are carried out.The CDR circuit based on phase interpolation is mainly composed of a sampler,an alignment and demultiplexer,a phase detector,a loop filter,and a phase interpolator.Among them,the phase detection module adopts an Alexander bang-bang phase detector,which only outputs the phase difference sign of the data and clock signal without outputting the magnitude of the phase difference.The loop filter uses a second-order digital filter,including two branches,a proportional path and an integral path,and has a certain frequency difference tracking capability.The phase interpolator adopts an inverter-based structure,and on this basis,a harmonic rejection filter is added which greatly improves the linearity of the phase interpolator.Finally,the overall CDR circuit is subjected to pre-imitation,layout design and post-imitation verification to ensure that the circuit performance meets the requirements.The layout area of the CDR circuit based on phase interpolation realized in this thesis is120*65?m~2.The circuit is simulated and verified by the AMS hybrid simulator.The post-simulation results show that at each process corner,when the power supply voltage is 0.8V,the input data rate is 6Gbps,and the clock frequency is 6GHz,the maximum jitter of the clock signal recovered by the CDR circuit is 10.6ps and the maximum power consumption is 15m W which meets the requirements of HDMI protocol.