Design Of High Power-efficiency,Low Jitter Clock Data Recovery Circuit

Serializer-Deserializer(SerDes)is commonly adopted to meet the requirement for high speed low BER data transmission.SONET/SDH is standard for those SerDes applied long reach communication through optical fiber.One of the key elements of SerDes is clock data recovery(CDR).This thesis concentrates on CDR design under SONET/SDH standard.This thesis has done the following work by adopting the methodology of IC circuit design as well as obeying relevant specification of SONET/SDH:This thesis presents a front-end data sampler by utilizing a current mode logic inductor-less d flip-flip.It has the ability of over sampling data with data rate up to 10 Gbps.In this thesis,a digital loop filter with variable gain is also presented.Variable gain can be adjusted according to the input jitter amplitude.Digital loop filter also consumes less die area compared to passive RC loop filter.The digital loop filter frequency tracking range is up to ±488ppm and its tracking accuracy is up to ± 122 ppm.Also,a phase interpolator suitable for either I/Q clock or 8-phase clock is presented in this thesis.There exist two modes in this phase interpolator.In mode I,phase interpolator utilizes I/Q clock to synthesize 8-phase clock.In mode II,phase interpolator utilized 8-phase clock with 45°offset to synthesize clocks.This design is under HLCM 55 nmdr process.the simulation result turns out that: The power efficiency is 5.424 mW/Gbps;the jitter of recovered data is 0.0372UI@625MHz.As for the components,the clock to Q time of the CML D flip-flop followed by CML buffer is 65 ps.The power consumption of the front-end sampler is 37.72 mW.The INL of phase interpolation is 11°.The maximum offset of DNL is 0.5LSB.The power consumption of PI is 14.32 mW.As for the digital circuit,DEMUX consume much power which is 2.058 mW.The power consumption of digital loop filter is 0.138 mW.