Research And Design Of A Ultra-High Speed Parallel Clock And Data Recovery Circuit

In ultra high speed optical systems, a parallel transmission technique has been used as an effective method to broaden the bandwidth. As the key technique of the ultra high speed(optical fiber)digital communication, the CDR(Clock and Data Recovery)technology has been studied continuously in order to achieve more suitable and prefect performance. In recent years, with the development of ultra high speed parallel optical interconnection, the parallel CDR applied in parallel optical interconnection become one of the major research areas.Firstly, some kinds of classical parallel CDR schemes are summarized, analyzed. The single channel CDR circuit carried on the parallel CDR has been analyzed and compared. The PLL(Phase-Locked Loop)-based CDR and PS(Phase Selection)/PI(Phase Interpolation)-based CDR has been emphatically studied.A 5Gb/s/ch 2-channel parallel CDR is designed in a standard 0.18μm CMOS process. The parallel CDR is realized by a PLL-based CDR and a PS/PI-based CDR. The PLL-Based CDR mainly includes a PFD(Phase Frequency Detector), a ring VCO(Voltage-Controlled Oscillator)and CPs(Charge Pump). The bootstrap reference technique and op amp is used to improve the charge-and-discharge current matching.The inductive shunt peaking technique is proposed to expand the bandwidth of the delay cell of the VCO. A pair of grounded-gata NMOS tubes are increased to improve tuning frequency and tuning range. At the same time, the linearity also has been improved. The PS/PI-based CDR mainly consists of bang-bang phase detector, PS/PI circuit,digital filter and digital controller. Compared with the traditional structure, two PS circuits have been reduced in the PS/PI circuit, thus improve the complexity and power consumption.In the parallel CDR, two orthogonal clocks are extracted from the input data of the PLL-based CDR, not only can complete the data recovery of the PLL-based CDR, but also serve as the reference clocks to complete the clock and data recovery in the follow-up channels of PS/PI CDRs.Compared with conventional circuits, The proposed scheme avoids mutual interference between VCOs. At the same time, the parallel CDR circuit does not need additional local reference clock and can be extended to multipath.The size of chip layout is 1.7×1.585mm2 and the core power consumption is 172.4mW. The simulation results showed that the peak-to-peak jitter of the recovered clock is 6.1ps and 8.1ps for 2parallel PRBS input data and the peak-to-peak jitters of the two recovered data are 8.7ps and 11.2ps.