The Design And Implementation Of A Clock Generator Based On DLL

Both Phase-Locked Loop(PLL)and Delay-Locked Loop(DLL)use phase-locked technology and are commonly used in clock generation circuits.Especially in circuits that require high clock signals,PLL or DLL is indispensable.DLL has advantages that PLL cannot compare with,especially DLL has good stability,low jitter and fast lock.Nowadays,the design of the PLL or DLL is more focused on the improvement of high frequency,high performance,low jitter and low power consumption.The DLL based on the Voltage-Controlled Delay Line(VCDL)is also of great concern because of its good performance.It can not only realize the phase division of the output clock signal and the input clock signal,but also can achieve frequency-multiplied output,thus meeting the needs of different clocks.Based on the 0.13 ?m process of a company,this paper designs a clock generator circuit based on the DLL.The DLL is mainly composed of four modules,namely,Phase frequency detector,charge pump,low-pass filter and voltage controlled delay line.The Phase frequency detector(PFD)adopts a new structure based on D flip-flop,which not only can effectively prevent the generation of dead zone,but also can make the input clock which first enters the PFD as feedback clock,the phase difference comparison between the reference clock and the feedback clock is omitted,thus the PFD phase discrimination of the Phase frequency detector becomes simple and uncomplicated,a comparator structure was also added to compare the output voltage of the low-pass filter with the standard voltage,and the comparator's result controlled the selection of the charge pump(CP)current.The VCDL mainly adopts push-pull delay cell structure,in this paper,two push-pull delay cells are composed of a push-pull delay cell,and a push-pull delay cell is composed of two push-pull delay cells,it can greatly improve the linear relation of the voltage controlled delay line and reduce the influence of too much or too little delay of the upper stage on the delay time of the next stage voltage controlled delay unit,the frequency multiplication circuit of this structure is simple.The goal of this paper is to input a 40 MHz reference clock and output a 640 MHz high frequency clock.At the same time,the PLL can meet the requirements of less than 5mW power consumption and no more than 500?m × 350?m layout area.Through the simulation before,after,process angle and Monte Carlo Simulation,the results basically meet the design requirements.