Research And Design Of A CMOS Phase Locked Loop For 5G Communication Rf Transceivers

With the rapid development of wireless communication technology and the increasing demand for short-distance high-speed communication,the fifth generation(5G)wireless communication system has emerged at the historic moment.Because the medium and low frequency bands of 5G wireless communication are already very crowded,and higher transmission rates require wider frequency band support,millimeter wave has become a good choice for 5G wireless communication due to its rich spectrum.Because the CMOS process has huge advantages in terms of cost,integration,and power consumption,the millimeter wave communication system using the CMOS process will be an inevitable result for the future development of wireless communication circuits.The phaselocked loop applied to high-speed systems has also become a research hotspot in recent years.Based on the 24.75?27.5GHz frequency band for the 5G wave band to be released by the Ministry of Industry and Information Technology of China as the target frequency band,an integer frequency division phase-locked loop is designed and implemented in this thesis.A rotary traveling wave voltage-controlled oscillator based on the transmission line model is designed in this thesis,which can generate multi-phase high-frequency oscillation signals.The oscillator is composed of a differential transmission line loop model and standing wave oscillation units.In the standing wave oscillator unit,a ?/4 differential transmission line instead of the traditional PMOS pair tube is used as a load to obtain higher oscillation frequency and lower power consumption.A feed-forward technology is used in the rotary traveling wave voltage-controlled oscillator to connect the standing-wave oscillator unit and the transmission line loop.At the same time,a short wire is introduced at the connection,so that the phase of the gate signal is ahead of the phase of the drain.As a result,the power consumption is reduced and the problem of uncertain circuit start direction is avoided,and the rotary traveling wave voltage-controlled oscillator is guaranteed to start counterclockwise.In order to obtain better phase noise performance and larger tuning range,a pair of switched capacitors are added to the standing wave oscillation unit,so that the rotary traveling wave voltage-controlled oscillator meets the requirements of the phase noise and tuning range.A programmable integer divider is designed in the divider chain,which consists of a static current mode logic frequency divider,a dual-modulus divider and a pulse swallow counter.The structure of the logic gate embedded in the flip-flop is adopted in the dual-mode frequency divider,so as to obtain a higher working speed.Asynchronous cascade subtraction is used in the pulse swallow counters to reduce the complexity and power consumption of the circuit.The counting ranges of the pulse counter and swallow counter are 30?35 and 0?7 respectively,and the frequency division ratio of the programmable frequency divider is 480 ? 560,so that the phase-locked loop output signal resolution is 100 MHz.A classic three-state structure is used in the phase frequency detector from the perspective of stability,and adds a delay loop to eliminate the "dead zone".The charge pump uses a source-switch structure to avoid charge sharing and introduces a rail-to-rail operational amplifier to achieve accurate matching of charge and discharge currents.The phase-locked loop,whose layout area is 675?m × 605?m,is designed in TSMC 65 nm CMOS process.The post-simulation results show that its tuning range is 24.1?27.6GHz,which can cover the frequency range of 24.75?27.5GHz,and the frequency modulation percentage is 14.7%.The total power consumption of the chip is 58.3m W,and the phase noise of-95.2d Bc/Hz @1MHz can be achieved from the output frequency of 25.6GHz.