A Design Of Charge-Pump Phase Lock Loop Based On CMOS Technics

As one of the important part of integrated circuit phase-locked loop shave been widely used in network communication and system clock, such as bit synchronization, frequency Synthesizer and clock recovery circuit. Although all sorts of phase-locked loops structures based on different application condition shave been presented, the work principle of them are similar. The system design of PLL is the most important problem for it is a feedback control system. The feasibility of a PLL is determined by its system design. The stability of a PLL is another important thesis about PLL design. There are a lot of factors that will affect the stability of a PLL and some of them are conflicting, so we must take a trade of strategy when we design it.This thesis presents a low power, steady two order charge pump phase-locked loop structure. The main work and innovation include:A stable CPPLL structure is proposed. The dead zone of PFD is discussed and resolved. The leakage current of CP is discussed and resolved. Adjustable design is added to the VCO design. The PD signal is added to achieve low power design. The whole simulation is based csmc 0.5μm CMOS process. Cadence spectre is used to input the circuit and simulate.One chapter in the thesis is system design and simulation, In which the whole design flow is introduced in detail. The simulation waves are presented too. Combined the design and the simulation, we will find some problems that disturb us and the answer of these problems are discussed. From the circuit structure and the result of simulation, we can see the designed CPPLL possess the characteristic of low power, high steady.