Research And Design Of Charge Pump Phase-Locked Loop For Clock Recovery Circuit

With the rapid development of integrated circuits,the charge pump phase-locked loop(CPPLL)has become an important part of the communication system because that it has these performances including high frequency,high precision and low jitter.Therefore,a CPPLL circuit for clock recovery circuit is designed by adopting SMIC 0.13?m CMOS process in this thesis.The main contents are as follows:Firstly,on the basis of analyzing the working principle of CPPLL,this thesis discusses the working principle of the core sub-modules of CPPLL that include phase frequency detector(PFD),charge pump(CP),low pass filter(LPF),voltage-controlled oscillator(VCO)and frequency divider(FD).Secondly,based on analyzing system architecture of the traditional CPPLL loop system,a system architecture of self-biased CPPLL is given in thesis.And,the mathematical model of the designed CPPLL system architecture is established by using Verilog-A language,and which verifies CPPLL's loop parameters including loop bandwidth,phase margin and lock time.Simulation results show that the designed CPPLL system architecture has these performances including the phase margin of 52°,the loop bandwidth of 2.95 MHz and the lock time of 2?s.Then,based on the SMIC 0.13?m CMOS process,this thesis designs the core sub-modules of the CPPLL that include PFD that overcomes the "dead zone" effect by adopting differential structure,self-adaptive self-bias CP with adjustable current,first-order loop filter by adopting MOS capacitor and equivalent output resistance of unity gain amplifier,current mode VCO with a load realized by diode connected PMOS transistor and cross coupled PMOS transistor,linear regulator LDO in order to increase swing and reduce noise and buffer module for shaping reference signal.Finally,based on the designed sub-modules of CPPLL design,a CPPLL system is designed in SMIC 0.13?m CMOS process.When the reference clock signal frequency is100 MHz and the output frequency is 1.25 GHz,the CPPLL system,whose loop is locked,has these performances that include the PFD's reset delay of 169 ps,the CP current mismatch rate of less than 1.6%,and the VCO phase noise of-81.41 d Bc/Hz@1MHz,the system lock time of 2?s,the control voltage of 638 m V and the output clock jitter of12.5ps.