The Design Of A Phase-Locked Loop Used In A DSP Clock System

Phase-locked loop (PLL) is a circuit which can synchronize its output signal with an input reference signal in frequency. It's a fundamental and very important module in analog and mixed-signal integrated circuits. Because of its ability of tracking, acquisition and operating as a narrow-band filter, PLL is widely used in many fields such as astronautics, communication, microprocessor, and so on. One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a very important module of microprocessor. With the development of integrated circuits and the emergence of SOC (System on a Chip) technology, PLL has played so important a role in VLSI circuits that it is worth researching and designing.In this paper, the research and design of a phase-locked loop utilized in DSP clock system are described in detail. First of all, the history of phase locked technology and the actuality of researches on it are introduced. Then, beginning with the fundamental principles of a phase-locked system, we build the mathematical model based on the architecture of the traditional analog PLL, and afterwards investigate some of its characters such as tracking, acquisition, noising, and stability. The system parameters are developed at the same time, and some universal conclusions on the theoretical analysis of PLL are reached. Since the circuit structure of this design is a charge-pump PLL, which is different from the traditional analog PLL in some respects, so we make a study of its operation principle, mathematical model and elementary characteristics, and introduce some of its unique characters simultaneously. At last, the design process of this project is described in detail, including the analysis and design of phase/frequency detector, charge pump, loop filter and voltage controlled oscillator, as well as the whole circuit system. All circuits are simulated with Hspice simulation software. The simulation results show that the PLL, based on standard 0.6 m CMOS technology, operates fairly well within the frequency range between 10MHz to 120MHz under the 5V power supply. The acquisition time is less than 10 s, and the power loss is less than 30 mW. All of the design targets are reached.