The Research And Design Of Key Circuit In 12GHz Phase-Locked Loop

In recent years,with the rapid development of wireless communication technologies,higher requirements have been placed on the performance of wireless communication devices,especially high-performance wireless transceiver front-ends.In the front-end of the transceiver,the PLL frequency synthesizer is a key module,which provides a local oscillator signal for the wireless transceiver system,and the quality of the local oscillator signal directly affects the performance of the transceiver.Therefore,high-performance PLLs have become the focus of people's research on transceiver front-end systems.This paper first expounds the main function of PLL in the wireless communication system,introduces the theoretical basis of the PLL,the current research status at home and abroad as well as the realization mode,and then analyzes the circuit of each module respectively.Finally,the circuit is designed and simulated on the basis of the TSMC 90 nm CMOS process.The main innovative work of this article can be summarized as follows:(1)The phase frequency detector designed in this paper is composed of digital logic circuits.By designing a new type of D flip-flop,the gate circuit is optimized,and the delay unit is improved so that the phase frequency detector has no dead zone,high frequency,and large scope of the phase and other advantages.After Cadence pre-simulation test,the simulation result is: Under the 1.2V power supply voltage,the phase detector has no phase-defining dead zone,and the phase-detection range is(-1.997?,+1.997?).(2)The charge pump circuit designed in this paper adopts a drain switch structure and has a faster switching speed.This circuit uses self-bias cascode current mirror and pseudo cascode technology,so that the minimum output voltage reduces a threshold voltage,the current mirror has a wider swing;while the use of voltage regulation cascode The technique reduces the change in the absolute current of the switch tube side;finally,the Dummy tube is introduced to eliminate clock feedthrough and charge injection.(3)The voltage controlled oscillator designed in this paper uses an LC structure suitable for operating at higher frequencies.This design reduces the noise introduced by the current source by improving Wilson's tail current source structure;using a MOS tube as a variable capacitor reduces current leakage and prevents the reference spur generated by the charge pump from entering the cavity;L,C value to meet the design requirements;the output stage uses a common source amplifier circuit as the output buffer stage,has a good isolation;input stage uses inductive noise reduction to reduce the phase noise.After Cadence pre-simulation test,the simulation results are: voltage control range 10.7~13.4GHz,center frequency 12.04 GHz,tuning range 22.4%,phase noise at center frequency-111.9dBc/Hz@1MHz,quality factor FoM-188,power consumption is 5.04 mW.(4)The three circuit modules designed in this paper are designed according to the design requirements and verified by the post-simulation.After the Spectre simulation verification,the performance meets the design requirements.