Design Of A Clock And Data Recovery Circuit Based On A Delay-and Phase-Locked Loop

Clock and data recovery(CDR)is a key technology in serial communication.Various tradeoffs existed depending on the real application scenario,such as output jitter and locking time.In this thesis,a hybrid CDR circuit which consists of Phase-locked loop(PLL)and Delay-locked loop(DLL)is designed for USB2.0 high-speed data transmission mode.This CDR featured low jitter and fast locking,and is of both practical and academic value.The proposed CDR circuit employs Voltage controlled oscillator(VCO)to recover the clock,and Voltage controlled delay Line(VCDL)to align data and clock.The PLL part provides a robust jitter tolerance while the DLL accelerates the locking speed.In this design,a combination of high-linearity charge-pump,balanced loading,pseudo-differential delay cells and loop voltage presetting are employed to reduce jitter and locking time.The detailed work is summarized as following:1)An analysis based on linear model and closed-loop transfer function of PLL,DLL,D/PLL is carried out,with a comparison of pros and cons of each architecture for CDR applications.This consists the theoretical foundation for following circuit design.2)Key building blocks,such as Hogge phase detector,charge pump,VCO,VCDL is designed in TSMC0.13?m CMOS technology,and verified by Spectre simulation.3)The whole design occupies a core area of 520*280 ?m2 in TSMC 0.13?m process.With 480MHz pseudo-random-binary-sequence(PRBS)input,the recovered data has a peak-to-peak jitter of 37ps,and a lockin time of 20ns.The whole chip dissipates 5.8mA under 1.2V supply voltage,and could satisfy the intended function and USB2.0 performance specifications.