Research And Design Of CMOS Charge Pump Phase-locked Loop

The Charge Pump Phase-Locked Loop(CPPLL)is a closed-loop feedback system that can realize high-precision output clock.The output clock of CPPLL has the advantages of high frequency,high precision and low jitter,so it has become an indispensable part of modern communication system.With the development of integrated circuit technology and packaging technology,the scale of chips is getting larger and larger and the size of chips is getting smaller and smaller,which provides higher requirements on the area,power consumption and jitter of the CPPLL.Based on those,a CPPLL was designed for Ethernet communication chip in this thesis.The main contents are as follows:Firstly,on the basis of analyzing the key sub-modules and working principle of CPPLL,these parameters of sub-modules of CPPLL were determined according to the design target.Mathematical models were constructed by using Verilog-A code,and the rationality of design target was verified by behavioral level simulation.Simulation results showed that the phase margin of the charge pump phase-locked loop system was 69.8 degrees,the loop bandwidth was 1.2MHz,and the locking time was 12.8?s.Secondly,a bandgap voltage reference was designed to provide the bias for the charge pump phase-locked loop system in SMIC 0.18?m CMOS process.Simulation results showed that the bandgap voltage reference achieved the output voltage of 1.2V and the temperature coefficient was 9.41ppm/°C in the range of-40°C to 125°C.An off-chip capacitive linear regulator circuit was designed to provide a supply voltage for the charge pump phase-locked loop system.Simulation results showed that the linear regulator achieved the output voltage of 1.8V,the load regulation of 0.12mV/mA and the line regulation of 6.8mV/V.Finally,a phase frequency detector,which could eliminate the "dead-zone effect",was designed by adopting an improved differential input structure.A low mismatch current charge pump was designed by adopting cascode current source,transmission gate and operational amplifier.A low phase noise ring voltage controlled oscillator was designed by adopting replica feedback bias technology and symmetrical load differential delay unit.A 5 frequency divider circuit with self-starting capability was designed by adopting D flip-flop and digital logic gate.Based on those,a charge pump phase-locked loop,which had a reference signal frequency of 25 MHz and an output signal frequency of 125 MHz,was designed in SMIC 0.18?m CMOS process.Simulation results showed that the reset delay time of phase frequence detector was 313 ps,the mismatch rate of charge pump current was 2% and the phase noise of voltage controlled oscillator was-108dBc/Hz@1MHz.The designed CPPLL system achieved the lock-in time of 13 ?s,the control voltage of 0.871 V and the output clock jitter of 251.4ps.