Design Of CPPLL Applied In High Speed Circuit

Phase-locked Loop(PLL) is core building block of clock generator of high-speed serial interface circuit and wireless communication system. With increase of information flow and system complexity, the requirements of operating rate, area, power, and jitter performance of PLL are getting higher and higher.This paper is designed for high-speed serial interface circuit system. First, the system architecture is analyzed, including linear model, noise model and stability of system. Basing on the system simulation software MATLAB the loop parameters of the system are calculated. The results of actual design of the transistor level circuit simulation and system model simulation are compared, and they are basically same.In circuit design, due to low input reference frequency, phase frequency detector(PFD) is based on a classic latch configuration. Phase dead zone has been eliminated by adjusting the delay of the feedback loop, while the blind zone has been reduced as much as possible, to improve the phase accuracy.Charge pump (CP) applies single-ended with operational amplifier clamping, in which the tail current source applies cascode structure with high voltage swing to obtain a high output impedance while maintaining a high output voltage swing and switch applies complementary switch to inhibit charge injection effect. Second order passive low pass filter is used to suppress high frequency noise and spurs of loop and filter noise of itself. Voltage-controlled oscillator (VCO) uses three order differential ring structure with cross pair for making output waveform level shifting faster, obtaining better symmetry to reduce the effect of phase noise. Due to the relatively high frequency division, divider uses pulse-swallow structure, the prescaler is based on TSPC D Flip-Flops structure, which increased the maximum operating frequency greatly. In this thesis both circuit design and layout are completed.The system circuit is fabricated in SMIC 0.13?m CMOS process. The post-simulation results show that the total power consumption is 5.4mA×3.3V, the lock time is less than 40?s, VCO output phase noise is -102dBc/Hz@1MHz and the max peak-peak jitter is 24.9ps@800MHz in TT process corner when the input reference clock frequency is 2MHz and VCO output signal frequency is 800MHz. The CPPLL occupies a chip area of 0.315mm×0.285mm.