A Design Of Wide-band Analog Delay-locked Loop

There are more and more applications about phase-locked loop in electronic circuits, and the technology is more and more mature, but the design of high-performance phase-locked loop is still difficult and hot. The Delay-Lock Loop that has some advantages which the phase-locked loop dose not have used widely in some case, so that it is the new hot spot.The three basic cells of DLL are Phase Detector(PD), Charge Pump(CP) and Voltage Controlled Delay Line(VCDL).The function of PD is detecting the phase of input signal and the final output signal, and controlling the CP next level by outputting the error square wave which includes the information of phase difference. The function of CP is converting phase difference signal of the output of PD to analog control voltage. It controls the charge and discharge of capacitance based on the phase difference signal to achieve the goals that the voltage of capacitance can change along with the phase difference signal. The VCDL is consisted of many delay cells and each one gets a same delay time which controlled by the output of PD. The difference of control voltage will get difference delay time. The total delay time in the delay line is one cycle. Then putting the signals which is being delayed combine with the input signal to the PD for phase comparing, thus, it is becoming a negative feedback loop circuit and can keep the input signal and output signal in the same frequent and phase.Analog and digital are the two realization ways of DLL, both of them have the advantages and disadvantages, and in this paper I only talk about the analog one. In this paper, I talk about those three parts in detail and give out their mathematical model and the system transfer function. Each part has many typical circuits, I have simulated the majority of them and gave out their results which are detailed analysis. I have putted forward some improved circuit by the results of simulation and the analyses in theory.In this paper, it has made some improve in the circuits of bias, delay cell and output, and have combined the advantages of two typical circuits together in the charge pump circuit. The function of bias is converting the control voltage output of CP to control voltage of VCDL. The control circuits introduced in this paper making full use of the two stage effect of MOSFET, can enlarge the range of current. It works better in the smaller technology. The feasibility in theory is also considered. The delay cell introduced in this paper adds another factor so that the factors of delay to be three, this factor not only can enlarge the range of delay but also makes the relationship of control voltage and delay time more liner. Combination of them can enlarge the range of lock greatly. In the circuit of output, the typical circuit has so large of current that may burn the MOSFET out when was in a large voltage of VCC. The circuits introduced in this paper holding on the majority ideas of it and improving some parts have smaller power consumption and more excellent performance. In the circuit of CP, using the op-amp to adjust the charge current, can eliminate the mismatch caused by the two stage effect of MOSFET. At the same time, the adding of MOSFET can provide a pathway for parasitic capacitance which may make influence to the function. The CP circuit which has took the advantages of them can meet the requirements of this paper.The simulations in this paper are in Cadence platform, the software of analog circuit design is IC5141, and the tool is Spectre. The technology library is tsmc18_rf. The circuit of DLL can be locked in1μs, the range is350MHz-700MHz.