Keyword [Voltage Controlled Delay Line] Result: 1 - 5 | Page: 1 of 1 1.  The Research And Implementation Of DLL In PHY Of DDR3 SDRAM Controller 2.  A Low Voltage SAR ADC Based On Voltage Controlled Delay Line And Bypass Logic 3.  The Radiation-harden Design Of Master-slave DLL For DDR3 SDRAM PHY 4.  The Design And Implementation Of A Clock Generator Based On DLL 5.  On-chip Capacitance PLL Frequency Synthesizer With Loop Stability Compensation Based On Voltage Control Delay Line   <<First  <Prev  Next>  Last>>  Jump to

Globe Thesis Copyright © 2023. All Rights Reserved. | Privacy | Copyright | Contribute | About | Contact | RSS