Research On Optimization Method Of Testing Time And Cost Of Three-dimensional System-on-chip

With the great breakthrough of integrated circuit manufacturing industry in the 21 st century,three-dimensional integration technology has become an important technology to lead the industry to continue Moore's law.Compared with traditional two-dimensional chips,three-dimensional chips have higher integration and more diverse functions.And the testing process of three-dimensional chips will face enormous challenges.The core problem of optimizing the testing process is to control the testing cost.In this paper,two optimization strategies are proposed for the mid-bond testing phase of three-dimensional system-on-chip.The main work is as follows:An optimized strategy is proposed for 3D SoC parallel testing in the mid-bond testing phase under power and parallelizable of cores constraints.Test time is greatly reduced and test cost is also reduced by reasonably allocating test access mechanism.In the testing process of 3D SoC,TAM resource of the chip is very limited.The method of this paper makes the core of each layer is in test schedule in order by the number of testing TAM resources occupied.By designing the corresponding test wrapper structure,we could redistribute the idle TAM resources under the current state of the system and internal scan chains of cores under test.It's in order to make cores waiting for scheduling advance into test phase,and reduce idle time in parallel testing.On the basis of the structure,we adjust the scheduling sequence of each core to make the test process meets all constraints.Experimental results on ITC'02 circuit show that compared with traditional methods,the method proposed reduces the test time more effectively.A three-dimensional system-on-chip test cost model considering core layered layout strategy and TSV bonding cost is proposed.On the basis of reasonable core distribution,the distribution of TSV is optimized,which greatly reduces the total test cost.In 3D system-on-chip scan chain design phase,the core is reasonably distributed to the wafers according to the length of the scanning chain by using the simulated annealing algorithm,which ensures that the scanning chain length of each layer of circuit is similar.And different core layout will affect the number and layout of TSV.In this paper,the shortest path algorithm is used to find the optimal layout of TSV.Under the proposed new test cost model,the factors such as test time and TSV bonding cost are synergistically considered to reduce the total cost of three-dimensional system-on-chip testing.The experimental results on ITC'02 circuit show that compared with the traditional core layered layout method,this test model considers more comprehensive factors and significantly reduces the total cost of testing.