Research On Low-cost And Low-power Test Techniques For Design For Testability Of SoC

With the rapid development of the design and process technology of integrated cir-cuit, the integration densities and system complexities of System-on-a-Chip (SoC) in-crease dramatically, and various intellectual property (IP) cores are integrated deeply in SoCs, which results in high test data volume (TDV) and excessive test power. The em-bedded IP cores can’t be accessed and controlled directly by external Input/Output (I/O) ports of SoCs, since they are integrated deeply in the SoC chips. Therefore, with the scale of the SoCs growing, the test controllability and observability of embedded IP cores are decreasing dramatically, since the I/O ports of SoC chips are limited. To address these problems, the design for testability (DFT) is introduced for improving test controllability and observability of SoC testing, which will bring about some additional test hardware and test application time (TAT). Recently, the growing high test cost and excessive test power are two serious concerns of SoC testing. Therefore, low-cost test and low-power test techniques have become topic researches in SoC testing area.To reduce the test hardware overhead, TDV, TAT and test power, this dissertation do researches on the low-cost and low-power test techniques for design for testability of SoC, which focus on the architecture of concurrent on-line built-in self-test (BIST), code-based test data compression and scan-shift test power. The major contributions and innovations can be summarized as follows.1) Based on the multilevel decoding logic, this dissertation proposes an improved ar-chitecture of concurrent on-line BIST and a low-cost optimization scheme. After an-alyzing the implementation and characteristics of the multilevel decoding logic, we propose a low-cost optimization scheme, which consists of input reduction, improved decoding and simulated annealing inputs swapping algorithms. Input reduction ap-proach is introduced to merge the compatible columns of the pre-computed test set in order to reduce the inputs for decoding. Then, an improved decoding algorithm is proposed, where the remaining columns that are less than the volume of a full group after decoding separation are not treated as a new group of themselves, which can cut down some redundant decoding logic. In addition, a modified simulated annealing inputs swapping heuristic algorithm is presented for optimizing the order of inputs, which can decrease some decoding logic. Experimental results indicate that the pro-posed optimization scheme can obtain about 20.96% and 8.38% hardware overhead reduction on average for special test set and another test set generated by ATAL ANTA ATPG tool, respectively, which reduces the test cost efficiently. Furthermore, an im-proved architecture of concurrent on-line BIST is proposed, which utilizes another multilevel decoding logic to verify the test responses. The proposed BIST can sup-port concurrent on-line testing for the circuit under test (CUT) whose detail can’t be obtained, such as hard IP cores, which makes it more adaptive.2) This dissertation presents two novel code-based test data compression schemes BMC and BM-8C, which are based on block merging and compatibility. TDV and TAT are two main factors of test cost. According to the characteristics of block merging and nine-coding (9C) test data compression techniques, a novel test data compres-sion scheme based on block merging and compatibility (BMC) is proposed. After partitioning the pre-computed test data into blocks equally and merging consecutive compatible blocks into merged blocks, BMC exploits the properties of inverse com-patibility between consecutive merged blocks, (inverse) compatibility between two halves of the encoding merged block itself to compress the test data. Experimental results show that BMC can achieve an average compression ratio up to 68.02% with about 9.37% TAT reduction on average. Furthermore, the properties including com-patibility between each half and all 0s or 1s are also introduced to encode the merged blocks in BM-8C scheme for further reducing TDV and TAT. Experimental results indicate that BM-8C can obtain an average compression ratio up to 68.14% and about 0.73% TAT reduction on average with respect to BMC. In addition, BMC and BM-8C are both test-independent compression techniques, where the decompression circuit doesn’t require to be modified according to the changes of the pre-computed test data, which makes them more attractive for SoC testing.3) For block-based coding test data compression, this dissertation proposes a novel inner-block reordering technique based on hybrid particle swarm optimization heuris-tic for further reducing TDV and TAT. The test compression ratio is mainly deter-mined by the inner-block order, since different inner-block orders may lead to differ-ent coding properties of test blocks, which can impact the test compression efficiency. Therefore, for further reducing TDV and TAT, a novel inner-block reordering tech-nique based on hybrid particle swarm optimization heuristic is proposed for finding an optimal inner-block order, which makes more merged blocks have properties to be compressed with shorter codewords. Experimental results show the efficiency that, for BMC and BM-8C, without any additional hardware introduced, the optimization scheme can achieve 0.38% and 0.43% higher compression ratio with about 0.82% and 2.12% TAT reduction on average, respectively.4) Based on scan partitioning, this dissertation presents an efficient scan-shift test power reduction approach, which includes selective Q-D connection and test vector reorder-ing. Scan partitioning can cut down the scan-shift process of the test data from the full scan chain into single scan segment through partitioning each scan chain into several scan segments, which can reduce the transitions of scan cells caused by scan-shift operations. A novel scan-shift test power reduction approach including selective Q-D connection and test vector reordering is proposed for further reducing scan-shift test power in this dissertation. After partitioning each scan chain into several scan segments evenly, selective Q-D connection is utilized to reconfigure every segment to reduce the transitions of scan cells caused by scan-shift process. Then, a novel test vector reordering algorithm based on ant colony optimization (ACO) heuristic is in-troduced to find an optimal order of test vectors, in order to decrease clashes between every two consecutive test vectors. Experimental results show that, the proposed optimization can achieve 6.39% and 7.64% scan-shift power reduction on average under 4 and 10 partitioned segments, respectively. Furthermore, the proposal can be acceptable for any scan-based testing architecture without affecting test quality, test cost, and/or performance of the CUT, which makes it more applicable.