The Research On NoC Communication Architecture Test And Ip Cores Test Scheduling Methods

In order to meet design requirements of the high intensive calculationapplications, as well as the method of the low power integration, more and morecomputing resources were integrated in a single chip, thus which formed System onChip (SoC). However, with the integration of integrated circuit to increase sharply,SoC which was based on shared bus architecture for communication is facing withinsurmountable bottlenecks, and already no longer meets demands on the futureSoC design. Therefore, the ideas of transplanting macro network technology in SoCwere put forward, computing resources were communicated with each otherthrough the network interconnection architecture, and communication andcomputing operations could be separated. The interconnection architecture isknown as Network on Chip (NoC). The global asynchronous local synchronizationcommunication mechanism and packet-switched communication technology isadopted in NoC, the shared bus architecture of the bottleneck problems hasthoroughly been solved from system structure.With the design method and manufacturing technology unceasing developmentand progress, test method has become one of the key problems in the process ofintegrated circuit product development. In order to improve the reliability of theintegrated circuit product, it must have been tested. Therefore, when NoC is tested,two aspects need be included, which are the communication architecture test and IPcores test. The main work of the dissertation is to reduce test time on testing thenetwork communication architecture and IP cores.The test on NoC communication architecture is in order to ensure thecorrectness and reliability of the IP cores communication. Therefore, a Built-inSelf-test method was proposed. Based on function failure model of router, theBuilt-in Self-test circuits were implemented, and the transmission paths of testpatterns were designed, so that the test patterns can be traversed the whole NoC toaccomplish test process. Experimental results show that the test time is effectivelyreduced, and test parallel is improved.Method of reusing NoC resources is used on IP cores test. Because of limited channel resources, therefore, test path, time and power need be comprehensivelybalanced. A clock frequency optimization algorithm was proposed by consideringthe test time and power factor to optimize IP cores the test clock frequency. Finally,IP cores test scheduling process was implemented under power constraint. In allcores shortest test time conditions, scheduling order of IP cores was selected.Experimental results show that the total IP cores test time and power is effectivelyreduced.