Research On Test Cost Optimization Method Of Three Dimensional Chip Under Power Constraint

With 3D chip manufacturing technology developing,the number of transistors and the complexity of functions increase drastically,which is severely challenging the 3D chip test.Long test time and large test data volume become the major problems in 3D chip test.Researching on the safe and fast chip test method is especially important for reducing the chip test cost.Starting from the power consumption safety,this thesis makes research on the test scheduling and test data compression of 3D chips.The main work is as follows:An optimized scheduling method based on time division multiplexing was proposed to optimize the test resources among layers and cores.Firstly,shift registers are arranged on each layer of 3D chip,and test frequency is divided properly among cores and layers under the control of shift registers on input data,then,the cores in different location can be tested in parallel;Secondly,a register allocation method based on greedy algorithm is used to reduce free test cycles in the test processing;Finally,DBPSO algorithm is used to find out the best 3D stack layout,the transmission potential of TS V can be entirely used to improve the test efficiency and reduce the test time.In addition,the time division multiplexing method can effectively reduce the risk of failure caused by local overheating.The experimental results show that the utilization rate of TAM was increased and the test time of the optimized 3D stack can be reduced,while the cost of testing is reduced.Based on the three-state signal,a test data compression method is proposed.Firstly,input simplification technique is used to streamline partial input of the original test set to reduce the number of definite bits in the test set;Secondly,the test vectors are divided into sub-vectors by multiple scans,the sub-vectors are coding by tri-state signal and the test vector is represented a shorter code word;Finally,the tri-state detection circuit is introduced,and the decompression structure in 2D chip and 3D chip are designed to decode the compressed data quickly.Experimental results show that the proposed method can achieve better compression ratio without higher area overhead and decode time,while the method can reduce shift-power.