The Research And Implementation Of Test Access Mechanism For SoCs

Quickly development of integrated circuit manufacturing technologyprompted the embedded system chip widely used, through the IP core reusetechnology with different function modules are integrated into a chip calledcalled system on chip, so is the micro system chip called SoC. At the same time,integrated circuit size and complexity increase and IP nuclear species diversity,that can realize and test the implementation of the strategy has become thedifficult problem of measuring chip SoC. In recent years, in order to solve theexcessive consumption of SoC test area and test time problem, proposed theSoCs test structure is nested in SoC with SoC form SoCs. In the SoCs teststructure, on the one hand, to test the package structure design of effectiveimplementation of the testability of the IP core, at the same time to minimize thenumber of register unit, so as to reduce the area consumption and shorten the testSoC overall test time; on the other hand, the SoC and SoCs test accessmechanism TAM science division and the rational allocation of limited TAMresources, grouping parallel test through the implementation of resourcemultiplexing strategy, has become the urgent need to solve the problem of testingSoC. Therefore, we should do some research of test strategy for SoCs teststructure, which may provide reference for relieving test cost increasingcomplexity of VLSI circuits and expensive in the future.In this paper, based on ITC ’02benchmark circuit SoC d695the hierarchicalstructure model is established, which is the test of SoCs system chip. Referencemicroprogram controller thought, with macro command as the guide, the use ofhardware software co-design ideas to design and optimize the structure of modeltest, the design of multi-level corresponding test access mechanism. In thehierarchical test structure, single stage with test access mechanism of traditionalSoC testing methods of realizing as the basis, according to the principle of scan test technology and IEEE1500test standard, considering the shell core nucleartest functions, nuclear scan chain balance optimization and test the total linedividing principles of SoCs parallel test unit Wrapper design, SoCs multistagetest access mechanism of TAM design, the proposed flexible allocation of theTAM testing strategy group SoCs bandwidth. For the test scheduling control,using the macro module control idea to realize. The SoCs hierarchical teststructure of divide and rule, parallel test, increase the flexibility, so as to improvetest efficiency, saving test time, to the present increasingly complex testimplementation is of great practical significance to study and optimization ofhierarchical SoCs.