The Research On Noc Communication Architecture Test Methods

With the rapid development of IC process more and more transistors are integrated in a single chip, which appeared in system on a chip.Increase in IC integration has brought many advantages, such as volume reduction, cost reduction and so on. However, as the circuit scale is growing, more and more processor units are integrated in a single chip, and the data-processing capacity of a chip is also growing, the inherent bottlenecks of the traditional on-chip system that based on bus architecture will become increasingly prominent, and can not meet the requirements of system designs. By the end of the twelfth century, some scholars have put forward the concept of on-chip network, the core idea is the computer network technology to migrate to chip design,that can solve the problems posed by the bus architecture from architecture. On-chip network has good spatial scalability and good parallel communications capabilities. Design methods, manufacturing methods and testing methods are the three components of IC development. However, in the early days of IC development, it is more attention focused on the design and manufacturing, and the logic of the early IC design and process technology is relatively simple, testing methodology study once in a position of not being taken seriously. With the rapid development of the IC design methods and technology, testing problem has become a factor that can not be ignored to improve the reliability of a product.The test of on-chip network are mainly two aspects:the test of communication architecture and the test of IP core. This paper is mainly targeted on the studing of the communications architecture testing,the main tasks are as follows:1.The article outlines the development of system on chip, the generated technical background of NoC and the research developments, and briefly describes the test-related knowledge of on-chip network and some of the existing solution to the test problems.2. In this paper, we present a division testing of network on chip interconnects (the communications architecture).The division testing is on the basis of pseudo-exhaustive testing,it divide the resources into four districts according to a certain method, and then use method of pseudo-exhaustive testing to test each partition respectively. Experiments show that this method can reduce the test time, the number of packages and the test power,and shrink the scope of error on chip compare with the pseudo-exhaustive testing as the chip size increasing. At the same time, this method can also ease some problems to a certain extent,such as the congestion and hot spots. In addition, the paper also present a method of locating error based on division testing, this method can locat the wrong routers or channels to the specific location of error partition.3. In this paper, we also present two kinds of improved methods to test the architecture of network on chip,base on the conclusion of the methods of multicast. The structures of all the routers in network on chip can be seen as similar, so we can use the same vectors to test the communication architecture of network on chip.In the two improved methods, all the test data packets are transmitted continuously, rather than waiting for the router to receive all packets and complete testing would and then be forwarded to. Experiment shows that, as size of the chip increasesing, these two improved methods have less test time and less number of packets than the method of multicast. And the larger that the size of chip increases, the more obvious the advantages. In the two improved methods, the latter is better than the earlier.