The Study On Low-Cost Testing Techniques For Core Based System-on-chip And Practical Implementation

Testing complex systems-on-chip (SoC) requires new test techniques and is necessary to the design process. Due to the continuous increase in chip complexity and transistor density, the cost of testing the chips will approach and even exceed the cost of design and manufacturing them. To alleviate the test cost problem, this research investigates methods which lead to low-cost test of core-based systems-on-a-chip without changing the embedded cores. Researching on the factors which drive the continuous increase in test cost, we can draw a conclusion that test compression provide a low-cost test solution for core based SoC. Test compression can reduce test data volume and test application time of SoC without losing fault coverage. Because the real worth of practicality, it has drawn significant attentions of academies and industries recently. Based on the different characteristic of test data, the test compression techniques can be classified into two categories, that is, test stimulus compression and test response compaction. This thesis conducts the research on both fields and presents several compression methods. The theoretical analysis and the experimental results for benchmark circuits demonstrated the efficiency of these techniques.The test stimulus can be showed in three dimensions:the z dimension represents the number of test vectors, the y dimension represents the sub-vectors, and the x dimension represents the average length of these sub-vectors. So two procedures and two test data compression methods are proposed which are capable of reducing the volume of test stimulus in different dimension respectively. (1) In z dimension, two dynamic compaction techniques have been proposed which can be added to a large variety of test generation procedures and have a low computational cost. In addition, dynamic test compaction can generate a smaller number of test vectors incorporated with the test generation process, and may also reduce test generation time. (2) In y dimension, a new technique to implement the decompressor by utilizing combinational circuits is proposed, which is efficient to reduce test cost in multiple scan chain designs. X bits in the test stimulus are filled then some scan slices will be compatible. The compatible scan slices can be obtained by the same external input. Thus, the proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. (3) In x dimension, this paper presents a compression and decompression scheme based on run-length codes for reducing the amount of test data, refer to hybrid run-length codes. It has the excellent advantages of high compression ratios, low area overhead and test power. Since the compression ratios strongly depend on the strategy of mapping don't cares in the original test set to zeros or ones, we also present an Iterative Sort Filling algorithm to find the best assignment method which minimizes the total size of the test data and achieves higher compression ratio.An efficient zero-aliasing compaction approach based on Cyclic Codes is proposed to reduce the volume of test response. The test response streams from many observation points can be compressed into a short signature by space compaction and time compaction of the method. The presented method contains space compaction and time compaction, and is independent of the design. It can also provide diagnosis capabilities by added some extra logic.Finally, in order to improve the practicability of the proposed algorithms and evaluate their performance again, we present an applied compaction network which includes most of the test methods presented by this thesis. The circuits of test have been implemented by FPGA, and used in the low-cost test scheme of the high performance DSP.