Research On Test Architectures Of Reusable IP Core And SOC (System On A Chip)

With the fast development of IC manufacturing techniques, SOC(System on a Chip) is gradually becoming true. Firstly, SOC integrates a complete system on the single chip, so it reduces the volume of the system; Secondly, SOC greatly improves the performance of the system by reducing the delay between chips in SOB(System on Board); Third, SOC uses core-based design methodology which shortens the design period and lowers the cost of chips. However SOC design also meets many challenges, test reuse is one of them. This dissertation systematically discusses the test architectures of reusable IP cores and SOC.The first problem of test reuse is the design of test architecture of reusable IP cores. The general architecture is that a test wrapper is added to the I/O ports of the IP cores. A kind of wrapper, namely tri-state wrapper, is put forward based on analyzing two kinds of wrappers, to be specific IEEE P1500 wrapper and TestShell from Philip. The architecture lets the different cores directly connect to the same test bus, and test data can be transferred from source or sink to I/O ports of cores within a single test clock period.The key of wrapper architecture is the design of wrapper cell. An improved wrapper cell is presented based on analyzing two kinds of wrapper cells in the dissertation. It adds a mux to the traditional PI500 wrapper cell, which not only can test the data path of wrapper cells, but also can resolve the problem of safe shifting of scan chains during shifting as well as reduces the dynamic test power during scan shifting.The second problem of test reuse is the design of SOC test architecture. SOC test architecture chiefly includes the design of TAM(Test Access Mechanism) which is used to transfer test data on chip and the design of chip-level test controller which is used to control the test of the cores on chip. Test bus is used extensively in TAM design. The principle of test bus is analyzed and general chip test architecture based on test bus is presented in the dissertation.There are many cores in a SOC. In order to realize so many tests for these cores, test scheduling should be done and a chip-level test controller should also be designed. A kind of chip-level test controller which can flexibly carry out the result of test scheduling is presented, which also takes chip test scheduling into account.SOC design is very complicated. Reusing IP cores in chip design is so far little. A kind of simple test control architecture is put forward according to such a fact. The architecture uses test bus-based TAM, and takes the problem of chip test into account during module design to make the design of chip-level test controller simpler.For the sake of reducing total test time and lowering the test cost, test scheduling should be done. Test scheduling is a typical NP-complete problem. The linear programming model of test scheduling is discussed and an algorithm of test scheduling based on Genetic Algorithms is presented in the dissertation.