Test Wrapper Optimization Technique Of 3D Embedded Cores

With the continuous progress in manufacture processes of integrated circuits, the feature size in transistors continue shrinking, interconnect delay has exceeded logic gate delay, which becomes a main bottleneck to improve system performance. Three Dimension Integrated Circuit (3D IC) can greatly reduce interconnect length and power consumption, appear as an effective method to solve the problem of interconnecting. Three Dimension System-on-a-chip (3D SoC) combines the advantage of 3D IC and System-on-a-chip (SoC), which has becoming the mainstream in the field of IC.3D SoC can be designed in coarse-granularity partition and fine-granularity partition. In coarse-granularity partition, each embedded core in a 3D SoC is still a 2D design. In fine-granularity partition, each embedded core consists of multiple circuit layers. This partition has tremendous advantage in reducing delay and improving chip performance. It also caused great challenges in optimizing 3D test wrapper. The design of test wrapper directly determines the test time of SoC. The thesis addresses test wrapper optimization technique to reduce test time of 3D SoC. The main contributions are briefly summarized as follows:1. This thesis presents a new technique to co-optimize total test time and hardware overhead under the constraints of TSVs and test pad number.3DTW0 (three dimension test wrapper optimization) technique are proposed to reduce pre-bond and post-bond test time of 3D SoC under the constraints of TSVs and test pad number. The proposed technique looks every pre-bond test wrapper chains as a whole and allocates it to layers and post-bond wrapper chains, which reduces total test time and hardware overhead. Balancing pre-bond and post-bond test wrapper chains simultaneously rather than separately is a key feature of the technique. Experimental results on ITC’02 benchmark circuit show that the proposed technique can effectively reduce total test time and slightly increases hardware overhead.2. This thesis presents a 3D test wrapper optimization technique under the constraints of TSVs number.To reduce total test time for 3D cores, this thesis proposed BGA method based on BFD (Best Fit Decreasing) and GA (Genetic Algorithm) algorithm under the constraints of TSVs number. The proposed technique firstly used BFD to balance the length of pre-bond wrapper chains to reduce pre-bond test time. Then, on the basis of optimization results of pre-bond wrapper chains, the GA was used to stitch pre-bond wrapper chains to form balanced post-bond wrapper chains under the constrained TSVs number to reduce post-bond test time. Besides, BGA method optimizes post-bond test wrapper chains on the basis of optimization results of pre-bond test wrapper chains, which reduces the hardware overhead for reconstruction. Experimental results of BGA method on ITC’02 benchmark circuit show that the total test time of the proposed technique slightly increases, but the hardware overhead is reduced.3. This thesis presents a 3D SoC optimization technique to reduce total test time.The first optimization purpose in this thesis is to reduce total test time of 3D SoC. This thesis proposes a optimization technique allocating scan elements to wrapper chains and circuit layers based on BFD and AL (Allocate Layer) algorithm. The technique maps scan elements to a plane, and BFD algorithm is employed to allocate scan elements to each wrapper chain to reduce post-bond test time. Secondly, AL algorithm is presented to allocate scan elements to each circuit layer to balance pre-bond wrapper chains, which can effectively reduce pre-bond test time and the number of TSVs. Besides, AL algorithm can also make the total length of scan elements in each layer as equal as possible. Experiment results on ITC’02 benchmark circuit show that the proposed technique can reduce total test time, and balance the length of total scan elements in each circuit layer of 3D embedded core.