Research On Design For Testability And Test Techniques Of Network-on-Chip System

The Network-on-Chip (NoC) is a new on-chip interconnect architecture. A System-on-Chip (SoC) whose interconnection is implemented by an on-chip network is called a Network-on-Chip system. Any new integrated circuits design technique will only be widely adopted if it is complemented by efficient and practical test methodologies. Testing a SoC whose interconnection is implemented by an on-chip network is challenging, and there is a pressing need for efficient test methodologies.In this dissertation, the research on key technique characteristics of NoC architecture and network protocols is focused on testing Network-on-Chip system (NoCs). And a lot of detailed research has been conducted on design for testability and test techniques to minimize the system test time and area overhead for satisfying the testing requirements of NoCs. The main works of the dissertation are as follows:1. Research on NoC model and NoC Simulation Testing Platform.To date, there has neither a uniform NoC architecture model nor NoC benchmarks to enable the objective comparison for new test methods with respect to effectiveness and efficiency. This has greatly exacerbated the test-related problem in NoCs. From the point of view of test methodologies, research is performed on NoC architecture and network protocol. Design for testability (DFT) architectures for router and network adapter were explored according to testing requirements of NoCs. A general NoC model is proposed and it can be synthesized in FPGAs. Furthermore, the NoC Simulation Testing Platform is proposed based on the general NoC model.2. Research on DFT and test techniques of NoC router and FIFOs.(1) NoC routers are tested by using the compatible IEEE 1500 wrapper architecture and the dedicated test access mechanism (TAM). Research was done on test response compaction in the following attributes:time versus space and linearity versus nonlinearity. Test response compaction may induce some loss of information. An aliasing probability analysis approach of time compactor was proposed by using the asymmetric error model and building a dual input fictitious time compactor. The proposed approach can be used to calculate and predict the exact aliasing probability of time compaction technique for any test input vector length.(2) Built-in self-test (BIST) architecture along with reusing NoC to transport test data was used to test FIFOs in NoC. The DFT-based FIFOs marching test algorithm with a linear-time complexity were proposed in the dissertation. The test algorithm with high fault coverage greatly reduces the total test time and on-chip area overhead in comparison to other FIFOs test algorithm. The dissertation explored unicast as well as multicast test data communication on 2-D msh and Torus network and presented a novel approach to transforming Hypercube topology into Torus topology. An example of transforming 4-D Hypercube into 4×4 2-D Torus is given in the dissertation and a multicast routing method used on Hypercube network is also applicable to the Torus network to transfer test data packets as well.3. Research on DFT and test techniques of non-hierarchical and hierarchical IP core embedded in NoCs.Test wrapper architecture is proposed in the dissertation and is applicable to non-hierarchical core in NoCs. The area overhead due to the implementation of the test wrapper used in NoCs is comparable to the overhead of a IEEE 1500 wrapper. A heuristic algorithm is used to configure the internal scan chains in core under test and wrapper boundary cells with considering test data packets latency in test time required to test cores. This algorithm can effectively minimize the maximum scan-in and scan-out lengths of the core under test and significantly reduce the number of test data packets and the total test data packets latency. The requirements and constraints on test modes of parent cores and child cores in hierarchical core were explored by analyzing the functionality of the elements of the wrapper and a new test mode and wrapper architecture were proposed for hierarchical core testing. In the NoCs, test scheduling is done to minimize the test time in a manner of nonpreemptive based on list scheduling with considering test parallelism and power consumption constraints.4. Research on the mixed-signal circuit test methodologies in NoCs.The NoC architecture model supporting mixed-signal circuit module is explored in the dissertation. The analog-to-digital converter is the essential components on the mixed signal circuit system. Aiming at analog-to-digital converter module testing, we proposed a BIST scheme for analog-to-digital converter based on a linear ramp signal and efficient output analysis. The proposed analysis method is an alternative to histogram-based analysis technique to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL, non-monotonic behavior can alao be detected with the proposed method. Two implementation options are proposed based on how much NoC hardware configuration resource is available.Finally, Theoretical studies and experimental results demonstrate the effectiveness of the proposed approach and obtained conclusions in the dissertation.