Research And Designof Test Access Mechanism And Test Scheduling Based On The SOC

With the progress of semiconductor process and design level, IP design industry has been entered the system-on-chip SOC era. Single chip integration of a greater number of transistors, can complete the more complex functions. This dissertation mainly discusses the general test architectures of SOC and expands on three sub problem, test wrapper design, test access mechanism design and test scheduling.System-on-ship SOC integrated circuits composed of processors, memories, and periripheral interface devices in the form of embedded cores, are now commonplace. First, the number of input/output pins in a chip cannot keep pace with the growth of the number of cores inside a chip. To reduce the hardware production and test cost, it is preferred to reduce the number of pins of a chip. This, unforthunately, implies that the test access time will be longer due to the delay time and limited test paths from the primary input/output to the core under test. This is called the TAM (Test Access Mechanism) limitation. The current SOC chips are two salient features of large-scale and large number of embedded IP core. The I/O ports of IP core can not be accessed directly by the SOC'pins for the IP core embedded in the SOC. Therefore, test access mechanism which provides a channel from test resource to test sink is needed;test wrapper is an interface between TAM and IP core, which can control the IP core operating mode; test scheduling is a process to determine the beginning and the end time of testing each IP core to minimize the total test time. As for SOC test, when the designer or integrator of SOC system have received the chip core, the most important problems need to be solved is to put the chip into market by test scheduling, which decides the test turns and resources of each chip core. Generally, we focus on the research on finding the optimal solution for solving the SOC test scheduling problems. The paper use the constructed neural network combined with genetic algorithm to find the optimal solutions within reasonable computing time. Through the researches mentioned above, the test architecture, optimization method and test scheme are provided for SOC to reduce both difficulties and costs of SOC test.