Research On Calibration Technology For Capacitance Mismatch In High Speed And High Resolution Pipelined ADC

With the development of communication technology,the requirement of ADC(Analog to Digital Converter)is becoming higher and higher.In many ADC architectures,Pipelined ADC is considered as an architecture with high speed,low power consumption and high precision.In recent years,the rapid development of semiconductor technology has not brought great improvement to the performance of Pipelined ADC.The main factors that affect the performance of the Pipelined ADC are the capacitance mismatch and the finite gain of the amplifier.The gain of the amplifier can be improved by increasing the number of stages of the amplifier or using the gain-boosting technique.Capacitance mismatch can be reduced by increasing the area of the capacitor,which also means the increase of power consumption.This is contrary to the low power requirements of consumer electronics.Therefore,it is more inclined to adopt the calibration algorithm to solve the mismatch problem.As the advantages of digital circuits in smaller process nodes are more pronounced,the calibration algorithm is more desirable through digital circuits.The calibration algorithm must include two processes,the first is the measurement of the error,and the second is the ADC output compensation and calibration.According to whether a separate calibration process is needed when ADC prepares for working,the calibration technology is divided into foreground calibration technology and background calibration technology.Compared with the foreground calibration technology,the background calibration technology is more robust to the environment,temperature and other factors because of the real-time correction.Therefore,the capacitance mismatch calibration technology in ADC is more inclined to the background calibration.At present,most of the digital calibration techniques using in Pipelined ADC with 1.5-bit/stage MDAC measures the errors by injecting pseudo-random code.And correct the results in the digital domain.The biggest drawback of this calibration technology is that the injected random vector greatly reduces the ADC input range.Compared to 1.5-bit/stage MDAC,>=2.5bit/stage MDAC has the advantages of lower power consumption while reducing the requirements for the process.However,the current research on capacitance mismatch calibration technology in Pipelined ADC with >= 2.5-bit/stage MDAC is focused on digital foreground calibration,and the technology for digital background calibration is hardly reported.This paper presents a digital background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC.And its feasibility,accuracy and stability are verified in MATLAB.Based on this technique,a 14-bit,40MS/s pipelined ADC is implemented.The chip is fabricated in X-fab 0.18 um CMOS process,occupied an active area of 4?4mm2,including on-chip decouple capacitors,with 110 m W power consumption at 3.3V.Chip test results show that the ENOB can be increased from 10.3 bits to 12.1 bits within one second.