Research On Digital Key Technologies Of A 20-bit Pipelined SAR ADC

The rapid development of the information age has promoted continuous innovation in computer and electronic technology,which puts forward higher requirements for the accuracy,speed,and power consumption of analog to digital converters in electronic systems.The traditional ADC architecture has been difficult to adapt to such needs,and the hybrid architecture ADC combines the advantages of multiple architectures.Pipelined SAR ADC is an architecture that combines Pipelined ADC and SAR ADC,enabling lower power consumption,higher accuracy,and faster conversion.However,this architecture also suffers from non ideal factors such as comparator misalignment,DAC capacitance mismatch,non ideal clock,inter stage residual amplifier gain error,and noise,which seriously affect the further improvement of the performance of Pipelined SAR ADCs.In order to overcome these problems,thesis deeply studies and analyzes the non ideal factors of Pipelined SAR ADC,and proposes a digital foreground correction technique.To achieve a fast and efficient digital correction process,further improving the performance of Pipelined SAR ADC,corresponding SPI modules and FFT modules have also been designed.Firstly,the working principle,performance indicators,and classification of ADC are briefly introduced.Then,the non ideal factors such as capacitance mismatch,comparator offset,non ideal clock,inter stage gain error,and noise existing in Pipelined SAR ADC are analyzed.The current correction techniques for offset mismatch are analyzed and reviewed.After that,a digital foreground correction technique is proposed to correct capacitance mismatches and gain errors.This correction technique achieves correction by comparing the bit weight deviation caused by capacitance mismatches at threshold points and detecting the residual difference step of the circuit to be calibrated to obtain the desired and actual error;The corresponding SPI module and FFT module are designed.Finally,based on 0.18 μm TSMC process layout design,the entire digital module is realized.After calibration,SNDR and SFDR were increased from 66.7 dB and 108.54 dB to 90.94 dB and 122.15 dB respectively;HD23 was increased from 109.23 dB to 129.21 dB;THD was increased from-100.55 dB to-122.74 dB;corresponding effective bit number ENOB was increased from 10.95-bits to 14.98-bits.The total power consumption of the entire digital module is only 1.1845 mw,while completing the formal verification and timing analysis of the digital module.