Study Of Digital Background Calibration Methods Of Pipelined ADCs

The advancement of modern electronic technology drives the demand for high performance ADCs.Compared with other structures of ADCs,the pipelined ADC has unique advantages in speed,precision and power consumption,which becomes one of the key points in the field of ADCs design and research in recent years.In order to further improve the performance of the pipelined ADC,considering the traditional design method of the analog circuit has been gradually becoming more difficult in the case of CMOS process improvement,using digital calibration technology to assist analog circuit design is becoming the trend of ADCs design.Digital background calibration technology,which not interrupt the normal operation of the pipelined ADC,can be used to calibrate the error of ADC timely and dynamically,and improve the performance of the pipelined ADC.Based on the 8-bit pipelined ADC design,various kinds of errors of the pipelined ADC are analyzed.To solve the main errors caused by capacitor mismatch and finite op-amp gain,a digital background calibration scheme is proposed.In this scheme,by injecting the PN sequence into the MDAC circuit of the calibrated stage,the inter-stage gain error resulting from two above errors can be measured,and the digital output is revised.The linear and non-linear errors of the pipelined ADC are calibrated,and the feedback can compensate the additional effect of the introduction of the PN sequence.The scheme is verified by Simulink modeling,and the simulation results show,with the calibration scheme,the ADC's SNDR and SFDR improved by 4dB and 21 dB,respectively.The verified calibration scheme is finally implemented by digital integrated circuit.Based on SMIC 0.18?m 1P6M technology,the RTL level coding,functional simulation,FPGA verification,logic synthesis,static timing analysis,formal verification,physical layout design and verification is completed in this thesis.The final digital circuit working frequency is 25MHz;chip area is about 1.5*1.5mm2;power consumption is less than 9mW.A digital background calibration scheme is proposed in this thesis.The scheme achieves the purpose of error calibration of capacitor mismatch and finite op-amp gain in the pipelined ADC,which enhance the performance of the pipelined ADC.The circuit has small area and low power consumption,which has practical significance.