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Calibration Technique Based On The Dither + The Dem 14-bit 150 Mb / Sec Sampling Pipelined Adc

Posted on:2011-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:K H LinFull Text:PDF
GTID:2208360305492578Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of the computer technology and communications technology, and the on growing needs of communication, the wireless communications have experience an unprecedented development in the worldwide areas. With the Business application of the broadband radio frequency technology and IP technology, the Fourth-generation base station gradually became the focus of the industry, showing the "multi-standard convergence, high integration, all IP, multi-carrier, green environmental protection" and other development. This multi-standard compatibility, intelligent development of technology is software-defined radio. It requires the base station receiver side of the analog and digital signal processing module into the antenna terminal. For achieving this high-performance base station, it is required that the ADC has the higher performance, such as having sufficient signal bandwidth to cover all of its operating frequency, having enough dynamic range in order to prevent adjacent channel signal obstruction, and having adequate signal to noise ratio,and so on. All these requirements are for the purpose of simplifying the increasingly complex structure of the base station.Pipeline ADC based on switched-capacitor circuits (SC) structure is the best option for covering the resolution and sampling rate range of the system. However, the errors caused by the process variation of capacitance mismatch, finite op amp gain and other non-ideal factors will directly affect the ADC performance. To achieve high performance, the calibration algorithms are usually used in the ADC systems. Digital background calibration has many nice features, such as scaling-down, good flexibility, high integration, and no disrupting the normal conversion process, so it becomes the mainstream of calibration.This thesis presents a 1.8V 14-bit 150MS/s Pipelined ADC with a novel digital background calibration technique based on Dither and DEM theory. Firstly the application environment and the development of ADC are briefly introduced. And then, the basic structure of the high-speed high-resolution pipelined ADCs is discussed from the system point of view. After that various non-ideal factors of the critical circuits are analysed and the specifications and system architecture is proposed. Then the key module circuit analysis and design, including the sample/hold circuit, the pipelined stages and the high precision reference voltage source driver is elaborated in detail from the circuit point of view. After which the digital background calibration combined with the structure of the system is disscued. In the last, the layout design and testing result is introduced.The proposed ADC is fabricated in SMIC 0.18μm one-poly six-metal CMOS Mixed-Signal process occupying 7.48mm2 die area and consuming 350mW (excluding output drivers) at 1.8V power supply and 150MHz sample rate. Measurements shows that, after calibration, the ADC achieves 14-bit linearity with +0.29/-0.28LSB DNL and +1.31/-1.13LSB INL. At 150 MS/s, the ADC acheives 86.6 dB SFDR and 70.7 dB SNDR for an input signal of 15.5 MHz, and the ENOB achieves 11.5 bits.
Keywords/Search Tags:ADC, Pipelined, Digital Background Calibration, Driver, Capacitor Mismatch, Opamp Gain Error
PDF Full Text Request
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