A Study Of The Calibration For The Errors In Pipelined ADC

As a link between the analog signal and the digital signal,Analog to Digital Converter(ADC) is a vital technique for the development of the integrated circuit. It plays an significant role in the process of digital image processing and so on. Pipelined ADC is a eclectic ADC on its accuracy, speed and power consumption. It is one of the ADC that be used most widely. Currently, the non-ideal factors capacitor mismatch error, the finite opamp gain error are the key factors affecting the performance of pipelined ADC. Therefore, we should research and rectify the error circuit to make higher precision.This paper presents a digital calibration that can calibrate the the finite opamp gain and capacitor mismatch error of pipelined ADC.It is important to study the circuit which can calibrate the error in order to improve the accuracy of pipelined ADC.Existing digital correction methods usually have some problems,such as complex circuit structure and the correction process is complicated. the digital correction methods described here is divided into two steps, firstly,accurate calibration coefficient is generated by the method of iteration, secondly, ADC operate normally, put the calibration coefficient into the circuit, calibrate the output of the digital code to accomplish the calibration. calibration method in this paper is simple in principle,the circuit structure is simple and calibrate exactly.In order to achieve the above-mentioned calibration method.This method is based on the design of 12 bit 40MSPS pipeline ADC. Put the capacitor mismatch error and finite gain error into the first two sub-stages, the first stage capacitor mismatch error is α1=-0.1,and the second capacitor mismatch error is α2=-0.05, the amplifier gain in the first stage is 80 d B, the amplifier gain in the second stage is 80 d B.other stages have no error.Put the digital calibration module into the model and start the simution.By comparing the parameters before the calibration and after the calibration., testing the feasibility and effect of the digital calibration method. To analyze the effect of different capacitor mismatch error on the circuit, we put different capacitor mismatch errors in the circuit and simulate time. Analyze the results of them.The results showed that after the digital calibration, the effective number of bits of the ADC improve from 7.6127 to 11.4666, Spurious-free dynamic range improve from 49.3736 d B to 77.2563 d B, Total harmonic distortion decrease from—48.6078 d B to-76.4697 d B, the performance of ADC greatly improved. Through the analysis of simulation results of different capacitor mismatch errors, we can conclude that the greater the error, the higher SNDR upgrade, and no matter how much the capacitor mismatch error, digital correction method can always increase the effective number of bits to 11 or more, so this calibration method can calibrate the capacitor mismatch error with large range,and can be applied in the pipelined ADC which has large capacitor mismatch error.